FET with wrap-around silicide and fabrication methods thereof
The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.
1. A semiconductor device, comprising:
a semiconductor fin protruding from a substrate;
an isolation structure surrounding sidewalls of the semiconductor fin;
a gate structure extending over a channel region of the semiconductor fin;
a source/drain (S/D) feature extending from an S/D region of the semiconductor fin, wherein the S/D feature is disposed adjacent the gate structure, and an extended portion of the S/D feature extends over the isolation structure; and
a silicide feature disposed on the extended portion of the S/D feature, wherein a portion of the silicide feature is disposed laterally between a sidewall of the gate structure and a sidewall of the S/D feature.
2. The semiconductor device of claim 1 , wherein the silicide feature further covers and lands on a top surface of the S/D feature within the S/D region of the semiconductor fin.
3. The semiconductor device of claim 1 , wherein the silicide feature completely covers and completely wraps around an outer surface of the extended portion of the S/D feature.
4. The semiconductor device of claim 1 ,
wherein the silicide feature forms a complete loop around the S/D feature in a first cross-section cut along the extended portion of the S/D feature in a lengthwise direction of the semiconductor fin,
wherein the silicide feature forms an incomplete loop around the S/D feature in a second cross-section cut along the S/D feature in a lengthwise direction of the gate structure.
5. The semiconductor device of claim 4 , wherein the incomplete loop is interrupted by a base fin portion of the semiconductor fin in the S/D region.
6. The semiconductor device of claim 1 , further comprising a spacer layer wrapping around the silicide feature, wherein the spacer layer is disposed laterally between the gate structure and the silicide feature.
7. The semiconductor device of claim 6 , further comprising an interlayer dielectric (ILD) layer over the spacer layer, wherein the ILD layer directly contacts the spacer layer.
8. The semiconductor device of claim 7 , further comprising a dielectric fin adjacent to the semiconductor fin, wherein a horizontal portion of the spacer layer separates the dielectric fin from the ILD layer.
9. The semiconductor device of claim 6 , further comprising an S/D contact penetrating through the spacer layer to land on the silicide feature.
10. A semiconductor device, comprising:
a semiconductor fin protruding from a substrate;
a shallow trench isolation (STI) structure adjacent a sidewall of the semiconductor fin;
an epitaxial source/drain (S/D) feature over the semiconductor fin;
a gate structure disposed over a channel region of the semiconductor fin;
a silicide layer disposed over the epitaxial S/D feature, wherein a portion of the silicide layer is disposed laterally between the gate structure and the epitaxial S/D feature; and
a spacer layer disposed over the silicide layer, wherein a portion of the spacer layer is disposed laterally between the gate structure and the silicide layer.
11. The semiconductor device of claim 10 , wherein the epitaxial S/D feature has a first portion directly above the semiconductor fin and a second portion directly above the STI structure, and the silicide layer directly contacts top, bottom, and sidewall surfaces of the second portion of the epitaxial S/D feature.
12. The semiconductor device of claim 10 , wherein the spacer layer has bottom portions that extend below the epitaxial S/D features.
13. The semiconductor device of claim 10 , wherein the epitaxial S/D feature includes multiple epitaxial layers, and the multiple epitaxial layers includes a first and a second epitaxial layer having different dopant concentrations.
14. The semiconductor device of claim 13 , wherein the first epitaxial layer surrounds the second epitaxial layer, and the first epitaxial layer directly contacts the silicide layer.
15. The semiconductor device of claim 10 , further comprising:
an interlayer dielectric (ILD) layer over the spacer layer; and
an S/D contact penetrating through the ILD layer and penetrating through a top portion of the spacer layer to land on a top surface of the silicide layer.
16. A semiconductor device, comprising:
a first and a second semiconductor fin protruding from a substrate;
an isolation feature over the substrate and over side surfaces of the first and second semiconductor fins;
a first and a second source/drain (S/D) feature over each of the respective first and second semiconductor fins, wherein the first and the second S/D features have extended portions that extend directly above the isolation feature; and
a first and a second silicide layer over each of the respective first and second S/D features, wherein each of the first and the second silicide layers fully wrap around the extended portions of each of the first and second S/D features.
17. The semiconductor device of claim 16 , further comprising:
a spacer layer wrapping around the first and the second silicide layers; and
an interlayer dielectric (ILD) layer over the spacer layer.
18. The semiconductor device of claim 17 , wherein the spacer layer covers upper tilted side surfaces and lower tilted side surfaces of the first and the second silicide layers.
19. The semiconductor device of claim 17 , further comprising:
a dielectric fin over the isolation feature and disposed between the first and second semiconductor fins, wherein the spacer layer separates the dielectric fin from the ILD layer.
20. The semiconductor device of claim 19 , wherein the isolation feature surrounds and directly contacts bottom and side surfaces of the dielectric fin.