Chip structure and method for forming the same
A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.
1 . A chip structure, comprising:
a substrate;
a first conductive line over the substrate;
an insulating layer over the substrate and the first conductive line;
a conductive pillar over the insulating layer, wherein the conductive pillar is formed in one piece, the conductive pillar has a lower surface, a protruding connecting portion, and a protruding locking portion, the protruding connecting portion protrudes from the lower surface and passes through the insulating layer and is in direct contact with the first conductive line, the protruding locking portion protrudes from the lower surface and is embedded in the insulating layer, the insulating layer separates the protruding locking portion from the substrate, the protruding locking portion is wider than the protruding connecting portion, and the protruding locking portion has a strip shape in a first top view of the conductive pillar and the first conductive line; and
a solder bump on the conductive pillar, wherein the solder bump is in direct contact with the conductive pillar.
2 . The chip structure as claimed in claim 1 , a width of the protruding connecting portion is less than a line width of the first conductive line.
3 . The chip structure as claimed in claim 1 , further comprising:
a second conductive line between the substrate and the conductive pillar, wherein a first top surface of the first conductive line is substantially level with a second top surface of the second conductive line, and the protruding locking portion of the conductive pillar is between the first conductive line and the second conductive line in a second top view of the conductive pillar, the first conductive line, and the second conductive line.
4 . The chip structure as claimed in claim 3 , wherein there is no conductive line between the first conductive line and the second conductive line.
5 . The chip structure as claimed in claim 1 , wherein a first longitudinal axis of the protruding locking portion is substantially parallel to a portion of the first conductive line under the conductive pillar in the first top view of the conductive pillar and the first conductive line.
6 . The chip structure as claimed in claim 5 , wherein the protruding connecting portion has a strip shape, and a second longitudinal axis of the protruding connecting portion is substantially parallel to the first longitudinal axis of the protruding locking portion in the first top view of the conductive pillar and the first conductive line.
7 . The chip structure as claimed in claim 1 , wherein the insulating layer is a single-layered structure.
8 . A chip structure, comprising:
a substrate;
a conductive line over the substrate;
an insulating layer over the substrate and the conductive line;
a conductive pillar over the insulating layer covering the conductive line, wherein the conductive pillar has a first sidewall and a second sidewall opposite to the first sidewall, the first sidewall and the second sidewall overlap the conductive line in a first top view of the conductive line and the conductive pillar, the conductive pillar has an upper surface having a first part and a second part, the first part is over the conductive line, the second part is not over the conductive line, the first part is higher than the second part, and the conductive pillar is in contact with the conductive line; and
a solder bump on the conductive pillar, wherein the solder bump is in contact with the conductive pillar.
9 . The chip structure as claimed in claim 8 , wherein the conductive pillar further has a protruding connecting portion and a protruding locking portion, the protruding connecting portion protrudes from a lower surface of the conductive pillar and passes through the insulating layer and is in direct contact with the conductive line, the protruding locking portion protrudes from the lower surface of the conductive pillar and is spaced apart from the conductive line, and the protruding locking portion is longer than the protruding connecting portion in a second top view of the protruding locking portion and the protruding connecting portion.
10 . The chip structure as claimed in claim 8 , wherein the conductive pillar having the first part of the upper surface and the conductive pillar having the second part of the upper surface have a substantially same thickness.
11 . The chip structure as claimed in claim 8 , wherein the second part of the upper surface has a substantially D shape, a substantially L shape, or a strip shape.
12 . A method for forming a chip structure, comprising:
forming a first conductive line over a substrate;
forming an insulating layer over the substrate and the first conductive line, wherein the insulating layer has a first recess, and the first recess has a strip shape in a first top view of the insulating layer;
forming a conductive pillar over the insulating layer covering the first conductive line, wherein the conductive pillar has a protruding locking portion in the first recess, the protruding locking portion has a trapezoid shape in a cross-sectional view of the conductive pillar, and a first portion of the insulating layer separates the protruding locking portion from the substrate; and
forming a solder bump on the conductive pillar, wherein the solder bump is in contact with the conductive pillar.
13 . The method for forming the chip structure as claimed in claim 12 , wherein the insulating layer further has a through hole, the through hole exposes a second portion of the first conductive line, the conductive pillar further has a protruding connecting portion in the through hole, and the protruding connecting portion is in direct contact with the second portion of the first conductive line.
14 . The chip structure as claimed in claim 13 , wherein a first bottom surface of the protruding connecting portion is closer to the substrate than a second bottom surface of the protruding locking portion.
15 . The method for forming the chip structure as claimed in claim 12 , wherein a linewidth of a second portion of the first conductive line under the conductive pillar is less than a width of the conductive pillar.
16 . The method for forming the chip structure as claimed in claim 12 , further comprising:
forming a second conductive line over the substrate while forming the first conductive line over the substrate, wherein the second conductive line is between the substrate and the conductive pillar, a first top surface of the first conductive line is substantially level with a second top surface of the second conductive line, and the protruding locking portion of the conductive pillar is between the first conductive line and the second conductive line in a second top view of the conductive pillar, the first conductive line, and the second conductive line.
17 . The method for forming the chip structure as claimed in claim 16 , wherein there is no conductive line between the first conductive line and the second conductive line.
18 . The method for forming the chip structure as claimed in claim 12 , wherein the first recess of the insulating layer extends across a sidewall of the solder bump in a second top view of the insulating layer and the solder bump.
19 . The method for forming the chip structure as claimed in claim 12 , wherein the first recess of the insulating layer is longer than the conductive pillar.
20 . The method for forming the chip structure as claimed in claim 12 , wherein a portion of the first recess of the insulating layer is not covered by the conductive pillar.