Granted Patent B2

US 12,477,776 · App. 18/750,751 · Granted Nov 18, 2025

Inventors: Paul A. Clifton (Palo Alto, CA); Andreas Goebel (Mountain View, CA); Walter A. Harrison (Palo Alto, CA)

Assignee: Acorn Semi, LLC

H10D30/6713B82Y10/00H10D30/43H10D30/62H10D30/6211H10D30/6219H10D30/6735H10D30/6757H10D62/121H10D62/151H10D64/251H10D64/647

Abstract

Claims (42)

1 . A transistor, comprising:

a stack of nanosheets, each having a channel region of a first semiconductor material disposed longitudinally between and electrically coupled with a semiconductor source region and a semiconductor drain region, wherein the semiconductor source region is included in a source stack comprising a source conductor contacting the semiconductor source region and extending along at least a portion of the semiconductor source region, the source conductor comprising a degenerately doped n-type semiconductor having an offset in conduction band energy between the degenerately doped n-type semiconductor and the semiconductor source region such that a conduction band minimum in the degenerately doped n-type semiconductor is at a higher energy than a conduction band minimum in the semiconductor source region; and

a gate stack having a gate conductor and a gate insulator wrapping completely around each of the channel regions of the nanosheets.

2 . The transistor of claim 1 wherein the semiconductor source region comprises silicon.

3 . The transistor of claim 2 wherein the degenerately doped n-type semiconductor comprises degenerately doped n-type gallium phosphide.

4 . The transistor of claim 2 wherein the degenerately doped n-type semiconductor comprises Ge.

5 . The transistor of claim 2 wherein the degenerately doped n-type semiconductor comprises AlAs.

6 . The transistor of claim 2 wherein the degenerately doped n-type semiconductor comprises AlSb.

7 . The transistor of claim 2 wherein the degenerately doped n-type semiconductor comprises ZnS.

8 . The transistor of claim 2 wherein the degenerately doped n-type semiconductor comprises ZnSe.

9 . The transistor of claim 2 wherein the degenerately doped n-type semiconductor comprises ZnTe.

10 . The transistor of claim 1 wherein the degenerately doped n-type semiconductor comprises degenerately doped n-type gallium phosphide.

11 . The transistor of claim 1 , wherein the first semiconductor material is an undoped semiconductor material.

12 . The transistor of claim 1 , wherein the source stack further includes an interfacial layer between the semiconductor source region and the source conductor, the interfacial layer comprising at least one epitaxial bilayer of group III and group V atomic monolayers.

13 . The transistor of claim 12 , wherein the semiconductor source region comprises a group IV semiconductor source region, one of the group V atomic monolayer is adjacent to and in contact with the semiconductor source region, and one of the group III atomic monolayers is adjacent to and in contact with the degenerately n-type doped semiconductor.

14 . The transistor of claim 13 , wherein the group IV semiconductor and the degenerately doped n-type semiconductor comprise different semiconductor materials.

15 . The transistor of claim 13 , wherein the group IV semiconductor and the degenerately doped n-type semiconductor each comprise a same semiconductor material.

16 . The transistor of claim 13 , wherein the interfacial layer comprises a monolayer of gallium (Ga) atoms and a monolayer of arsenic (As) atoms, and the group IV semiconductor and the degenerately doped n-type semiconductor each comprise germanium (Ge).

17 . The transistor of claim 1 , wherein a Schottky barrier between the source conductor and the semiconductor source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.

18 . The transistor of claim 17 , wherein the free charge carriers are electrons.

19 . The transistor of claim 17 , wherein the free charge carriers are holes.

20 . The transistor of claim 17 , wherein the Schottky barrier between the source conductor and the semiconductor source region is between −0.1 eV and −0.5 eV.

21 . The transistor of claim 1 , wherein the semiconductor source region comprises silicon, germanium, silicon carbide, or an alloy comprising two or more of silicon, germanium, carbon and tin.

22 . The transistor of claim 1 wherein the semiconductor source region is not intentionally doped.

23 . The transistor of claim 1 wherein the semiconductor drain region is not intentionally doped.

24 . The transistor of claim 1 wherein the semiconductor source region and the semiconductor drain region are not intentionally doped.

25 . The transistor of claim 1 wherein the transistor is a field effect transistor.

26 . A transistor, comprising:

a stack of nanosheets, each having a channel region of a first semiconductor material disposed longitudinally between and electrically coupled with a semiconductor source region and a semiconductor drain region, wherein the semiconductor source region is included in a source stack comprising a source conductor contacting the semiconductor source region and extending along at least a portion of the semiconductor source region, the source conductor comprising a degenerately doped p-type semiconductor having an offset in valence band energy between the degenerately doped p-type semiconductor and the semiconductor source region such that a valence band maximum in the degenerately doped p-type semiconductor is at a lower energy than a valence band maximum in the semiconductor source region; and

a gate stack having a gate conductor and a gate insulator wrapping completely around each of the channel regions of the nanosheets.

27 . The transistor of claim 26 wherein the transistor is a field effect transistor.

28 . The transistor of claim 26 , wherein the source stack further includes an interfacial layer between the semiconductor source region and the source conductor, the interfacial layer comprising at least one epitaxial bilayer of group III and group V atomic monolayers.

29 . The transistor of claim 28 , wherein the semiconductor source region comprises a group IV semiconductor source region, one of the group V atomic monolayer is adjacent to and in contact with the degenerately doped p-type semiconductor, and one of the group III atomic monolayers is adjacent to and in contact with the semiconductor source region.

30 . The transistor of claim 29 , wherein the group IV semiconductor and the degenerately doped p-type semiconductor comprise different semiconductor materials.

31 . The transistor of claim 29 , wherein the group IV semiconductor and the degenerately doped p-type semiconductor each comprise a same semiconductor material.

32 . The transistor of claim 29 , wherein the interfacial layer comprises a monolayer of gallium (Ga) atoms and a monolayer of arsenic (As) atoms, and the group IV semiconductor and the degenerately doped p-type semiconductor each comprise germanium (Ge).

33 . The transistor of claim 26 , wherein the semiconductor source region comprises germanium and the degenerately doped p-type semiconductor comprises degenerately doped p-type silicon.

34 . The transistor of claim 26 wherein the semiconductor source region comprises germanium and the degenerately doped p-type semiconductor comprises degenerately doped p-type silicon germanium.

35 . The transistor of claim 26 , wherein the semiconductor source region comprises silicon, germanium, silicon carbide, or an alloy comprising two or more of silicon, germanium, carbon and tin.

36 . The transistor of claim 26 wherein the semiconductor source region is not intentionally doped.

37 . The transistor of claim 26 wherein the semiconductor drain region is not intentionally doped.

38 . The transistor of claim 26 wherein the semiconductor source region and the semiconductor drain region are not intentionally doped.

Assignments (4)

Continuity (8)

References Cited (400)