Preserving access to optical components on a wafer package with sacrificial cap
The present disclosure relates to packaging techniques in connection with packaging electrical and optical components within circuit packages. For example, one or more examples described herein involve techniques for packaging an electro-photonic circuit while preserving access to a grating coupler, which may involve using a sacrificial cap in conjunction with a unique overmolding process.
1 . A method for packaging an electro-photonic circuit, comprising:
obtaining a substrate having an optical region configured to allow light to exit or enter from a top surface of the substrate;
positioning a sacrificial cap on the top surface of the substrate covering the optical region, wherein the sacrificial cap includes a top portion and a recess formed therein under the top portion, and wherein the recess is positioned over the optical region when the sacrificial cap is positioned over the top surface of the substrate;
depositing an overmold over the top surface of the substrate and over the sacrificial cap; and
grinding down a top surface of the overmold, wherein grinding down the top surface of the overmold includes grinding down the top portion of the sacrificial cap to expose the recess, wherein the recess provides a void over a substantial portion of the optical region prior to grinding.
2 . The method of claim 1 , wherein exposing the recess exposes an optical path to the optical region.
3 . The method of claim 1 , further comprising coupling a plurality of optical fibers to the optical region using an optical interface component.
4 . The method of claim 3 , wherein the optical interface component is a fiber array unit (FAU).
5 . The method of claim 1 , wherein:
the substrate comprises bumps on the top surface of the substrate and waveguides formed within the substrate; and
the method further comprises, prior to depositing the overmold over the top surface of the substrate, disposing one or more electronic components on the top surface of the substrate, wherein disposing the one or more electronic components over the top surface of the substrate comprises electrically connecting the one or more electronic components to the bumps on the top surface of the substrate to form electro-optical paths to and from the one or more electronic components to the optical region via the waveguides formed within the substrate.
6 . The method of claim 1 , wherein obtaining the substrate comprises obtaining a substrate comprising bumps on the top surface of the substrate, waveguides formed within the substrate, one or more electronic components disposed on the top surface of the substrate and electrically connected to the bumps on the top surface of the substrate, and electro-optical paths to and from the one or more electronic components to the optical region via waveguides formed within the substrate.
7 . The method of claim 1 , wherein, prior to grinding down the top surface of the overmold, the top portion of the sacrificial cap has a thickness of greater than 25 microns.
8 . The method of claim 1 , wherein a thickness between a top and bottom surface of the sacrificial cap prior to grinding down the top surface of the overmold is less than 1000 microns.
9 . The method of claim 1 , wherein the sacrificial cap being positioned over the top surface of the substrate covering the optical region prevents the overmold from flowing between the sacrificial cap and the substrate.
10 . The method of claim 1 , wherein the sacrificial cap and the overmold that is deposited over the substrate are made from a same material.
11 . The method of claim 1 , wherein the sacrificial cap and the overmold that is deposited over the substrate are made from different materials.
12 . The method of claim 1 , wherein the substrate is a wafer.
13 . The method of claim 1 , wherein the sacrificial cap includes one or more openings between an exterior of the sacrificial cap and the recess, the one or more openings being configured to allow gas to escape from the recess under thermal expansion of the sacrificial cap.
14 . The method of claim 13 , wherein the one or more openings are sized to allow gas to escape from the recess without allowing the overmold to penetrate the one or more openings and flow into the recess.
15 . A method for packaging an electro-photonic circuit, comprising:
obtaining a photonic integrated circuit (PIC) wafer comprising:
an optical region near a top surface of the PIC wafer configured to allow light to enter and exit the PIC wafer; and
optical transmitter and receiver portions in optical communication with the optical region, the optical transmitter and receiver portions having electrical interconnects to the top surface of the PIC wafer in a portion that does not extend into the optical region;
positioning a sacrificial cap over the top surface of the PIC wafer covering the optical region, wherein the sacrificial cap includes a top portion and a recess formed therein under the top portion, and wherein the recess is positioned over the optical region when the sacrificial cap is positioned over the top surface of the PIC wafer;
depositing an overmold over the PIC wafer and over the sacrificial cap; and
grinding down a top surface of the overmold, wherein grinding down the top surface of the overmold includes grinding the top portion of the sacrificial cap to expose the recess, wherein the recess provides a void over a substantial portion of the optical region prior to grinding.
16 . The method of claim 15 , wherein exposing the recess exposes an optical path to the optical region.
17 . The method of claim 15 , further comprising coupling a plurality of optical fibers to the optical region using an optical interface component.
18 . The method of claim 17 , wherein the optical interface component is a fiber array unit (FAU).
19 . The method of claim 15 , wherein:
the PIC wafer comprises bumps on the top surface of the PIC wafer and waveguides formed within the PIC wafer; and
the method further comprises disposing one or more electronic components on the PIC wafer, wherein disposing the one or more electronic components on the PIC wafer comprises connecting electrical contacts of the one or more electronic components to the bumps on the top surface of the PIC wafer and forming electro-optical paths to and from the one or more electronic components to the optical region via the waveguides formed within the PIC wafer.
20 . The method of claim 15 , wherein obtaining the PIC wafer comprises obtaining a PIC wafer comprising bumps on the top surface of the PIC wafer, waveguides formed within the PIC wafer, one or more electronic components disposed on the top surface of the PIC wafer and electrically connected to the bumps on the top surface of the PIC wafer, and electro-optical paths to and from the one or more electronic components to the optical region via waveguides formed within the PIC wafer.
21 . The method of claim 15 , wherein, prior to grinding down the top surface of the overmold, the top portion of the sacrificial cap has a thickness of greater than 25 microns.
22 . The method of claim 15 , wherein a thickness between a top and bottom surface of the sacrificial cap prior to grinding down the top surface of the overmold is less than 1000 microns.
23 . The method of claim 15 , wherein positioning the sacrificial cap over the top surface of the PIC wafer covering the optical region prevents the overmold from flowing between the sacrificial cap and the PIC wafer.
24 . The method of claim 15 , wherein the sacrificial cap is made from a same overmolding material as the overmold that is deposited over the PIC wafer.
25 . The method of claim 15 , wherein the sacrificial cap is made from a different overmolding material as the overmold that is deposited over the PIC wafer.
26 . The method of claim 15 , wherein the sacrificial cap includes one or more openings between an exterior of the sacrificial cap and the recess, the one or more openings being configured to allow gas to escape from the recess under thermal expansion of the sacrificial cap.
27 . The method of claim 26 , wherein the one or more openings are sized to allow gas to escape from the recess without allowing the overmold to penetrate the one or more openings and flow into the recess.