Apparatus and method for selectively controlling display pixels
A pixel driving circuit for a display device includes a data driving circuit configured to output control signals indicating operation modes and a data signal indicating image data through a column line or a row line, and an array of a plurality of pixels, each pixel including a light-emitting element, and a pixel-embedded memory configured to receive the data signal from the column or row line via a first signal path, and configured to store the image data to drive the light-emitting element of a pixel, and a signal distributor configured to connect the first signal path to or disconnect the first signal path from the column or row line based on the operation modes.
1 . A pixel driving circuit for a display device, comprising:
a data driving circuit configured to output control signals indicating operation modes and a data signal indicating image data through a column line or a row line; and
an array of a plurality of pixels, each pixel including:
a light-emitting element, and
a pixel-embedded memory configured to receive the data signal from the column or row line via a first signal path, and configured to store the image data to drive the light-emitting element of a pixel; and
a signal distributor configured to connect the first signal path to or disconnect the first signal path from the column or row line based on the operation modes,
wherein the operation modes comprise a partial update mode and a partial non-update mode;
wherein the signal distributor is configured to connect the first signal path to the column or row line based on the partial update mode; and
wherein the signal distributor is configured to disconnect the first signal path from the column or row line based on the partial non-update mode.
2 . The pixel driving circuit according to claim 1 , wherein
a main memory configured to store image data to illustrate images for the array of the plurality of pixels; and
a processor configured to compare two sequential images and based on a result of the comparison, to determine:
a first region of the array of the plurality of pixels to update pixel-embedded memories of pixels within the first region; and
a second region of the array of the plurality of pixels not to update pixel-embedded memories of pixels within the second region.
3 . The pixel driving circuit according to claim 2 , wherein
the data driving circuit is configured to output a first control signal indicating the partial update mode to pixels within the first region, and a second control signal indicating the partial non-update mode to the pixels within the second region.
4 . The pixel driving circuit according to claim 3 , wherein
the first control signal comprises a first number of toggles, and
the second control signal comprises a second number of toggles.
5 . The pixel driving circuit according to claim 1 , wherein
the pixel-embedded memory comprises:
a data memory storing multi-bit digital data representing a gradation level for the light-emitting element.
6 . The pixel driving circuit according to claim 4 , further comprising a counter configured to count a number of toggles of the first control signal or the second control signal.
7 . The pixel driving circuit according to claim 6 , wherein:
when a column line signal indicates the partial update mode, the column line signal comprises a first signal pattern including N toggle cycles occurring within a logic-low time period of a row line signal; and
when the column line signal indicates the partial non-update mode, the column line signal comprises a second signal pattern including M toggle cycles occurring within the logic-low time period of the row line signal, wherein M is less than N.
8 . The pixel driving circuit according to claim 6 , wherein:
the signal distributor is configured to selectively route signals based on reset signals generated by a reset controller,
wherein the reset controller is configured to:
generate a first reset signal indicating a termination of the partial update mode when the column signal performs M toggle cycles within a logic-low time period of the row signal, wherein M is greater than 3; and
generate a second reset signal indicating a termination of writing the image data to the pixel-embedded memory when the column signal performs N toggle cycles within the logic-low time period of the row signal, wherein N is greater than M.
9 . A method performed by a pixel driving circuit for a display device, the pixel driving circuit including a data driving circuit and an array of a plurality of pixels, each pixel including a light-emitting element, a pixel-embedded memory, and a signal distributor, the method comprising:
outputting, by the data driving circuit, control signals indicating operation modes and a data signal indicating image data through a column line or a row line;
connecting, by the signal distributor, a first signal path between the column line or the row line and the pixel-embedded memory based on a partial update mode included in the operation modes;
disconnecting, by the signal distributor, the first signal path from the column line or the row line based on a partial non-update mode included in the operation modes; and
in response to the first signal path being connected, receiving, by the pixel-embedded memory, the data signal via the first signal path and storing the image data, wherein the stored image data is used to drive the light-emitting element of the pixel.