IP Library › Granted Patent US 6,859,158
Granted Patent B2
US 6,859,158 · App. 10/653,251 · Granted Feb 22, 2005

Analog-digital conversion circuit

Assignee: Sanyo Electric Co., Ltd.
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Quick Facts
Patent No.
US 6,859,158
App. No.
10/653,251
Granted
Feb 22, 2005
Kind
B2
Abstract

An operational amplifier, a sub A/D converter, a D/A converter, and an operation amplifier in a first stage circuit operate in response to a clock signal. An operation amplifier, a sub A/D converter, a D/A converter, and an operation amplifier in a second stage circuit operate in response to a clock signal having a frequency three times as high as that of the first clock signal. An analog signal output from the operational amplifier in the first stage is applied to an input node in the second stage circuit through a switch. An analog signal output from an operational amplifier in the second stage circuit is applied to an input node in the second stage circuit through a switch.

Claims (57)

1. An analog-digital conversion circuit, comprising:

a first circuit having first and second nodes;

a selector that selectively applies one of an input analog signal and an analog signal at said second node to said first node; and

a control device that controls said selector,

said first circuit comprising:

a first operational amplifier that amplifies an analog signal from said first node;

a first analog-digital converter that converts an analog signal from said first node into a digital signal, the analog signal input to said first operational amplifier being the same as the analog signal input to said first analog-digital converter;

a first digital-analog converter that converts the digital signal output from said first analog-digital converter into an analog signal; and

a first differential amplifier that amplifies the difference between the analog signal from said first operational amplifier and the analog signal output from said first digital-analog converter and outputs the amplified difference to said second node,

said control device controlling said selector so that after the input analog signal is applied to said first node, conversion operation by said first analog-digital converter, conversion operation by said first digital-analog converter, and amplifying operation by said first differential amplifier are carried out for a prescribed number of cycles.

2. The analog-digital conversion circuit according to claim 1 , wherein

said first circuit further comprises a first operational amplifier that amplifies the analog signal at said first node and applies the amplified signal to said first differential amplifier.

3. The analog-digital conversion circuit according to claim 1 , further comprising a second circuit provided preceding said first circuit by at least one stage through said selector,

said second circuit comprising:

a second analog-digital converter that converts an input analog signal into a digital signal;

a second digital-analog converter that converts a digital signal output from said second analog-digital converter into an analog signal; and

a second differential amplifier that amplifies the difference between said input analog signal and the analog signal output from said second digital-analog converter and outputs the amplified difference to said first circuit through said selector.

4. The analog-digital conversion circuit according to claim 3 , further comprising a second operational amplifier that amplifies said input analog signal and applies the amplified signal to said second differential amplifier.

5. The analog-digital conversion circuit according to claim 1 , wherein

said control device comprises a signal generator that generates a clock signal and a control signal,

said first analog-digital converter, said first digital-analog converter, and said first differential amplifier in said first circuit operate in response to the clock signal generated by said signal generator, and

said selector responds to the control signal generated by said signal generator to select between a state in which the input analog signal is applied to said first node and a state in which the analog signal at said second node is applied to said first node.

6. The analog-digital conversion circuit according to claim 5 , wherein

said control signal has a first frequency, said clock signal has a second frequency that is an integral multiple of said first frequency.

7. The analog-digital conversion circuit according to claim 5 , further comprising a changing device that changes the frequency of the clock signal generated by said signal generator.

8. The analog-digital conversion circuit according to claim 7 , wherein

said signal generator comprises a phase locked loop having a frequency divider, and

said changing device comprises a frequency dividing factor setting device that sets a frequency dividing factor by said frequency divider in said phase locked loop.

9. The analog-digital conversion circuit according to claim 3 , wherein

said control device comprises a signal generator that generates first and second clock signals and a control signal,

said first analog-digital converter, said first digital-analog converter, and said differential amplifier in said first circuit operate in response to the first clock signal generated by said signal generator,

said second analog-digital converter, said second digital-analog converter, and said second differential amplifier in said second circuit operate in response to the second clock signal generated by said signal generator, and

said selector responds to the control signal generated by said signal generator to select between a state in which the analog signal output from said second differential amplifier in said second circuit is applied to said first node and a state in which the analog signal at said second node is applied to said first node.

10. The analog-digital conversion circuit according to claim 9 , wherein

said control signal has a first frequency, said first clock signal has a second frequency that is an integral multiple of said first frequency, and said second clock signal has said first frequency.

11. The analog-digital conversion circuit according to claim 9 , wherein

said control device further comprises a changing device that changes the frequency of the first clock signal generated by said signal generator.

12. An analog-digital conversion circuit, comprising:

a first circuit having first and second nodes;

a selector that selectively applies one of an input analog signal and an analog signal at said second node to said first node; and

a control device that controls said selector,

said first circuit comprising:

a first operational amplifier that amplifies an analog signal from said first node;

a first analog-digital converter that converts an analog signal from said first node into a digital signal;

a first digital-analog converter that converts the digital signal output from said first analog-digital converter into an analog signal; and

a first differential amplifier that amplifies the difference between the analog signal from said first operational amplifier and the analog signal output from said first digital-analog converter and outputs the amplified difference to said second node,

said control device controlling said selector so that after the input analog signal is applied to said first node, conversion operation by said first analog-digital converter, conversion operation by said first digital-analog converter, and amplifying operation by said first differential amplifier are carried out for a prescribed number of cycles.

13. An analog-digital conversion circuit, comprising:

a first circuit having first and second nodes;

a selector that selectively applies one of an input analog signal and an analog signal at said second node to said first node; and

a control device that controls said selector,

said first circuit comprising:

a first operational amplifier that amplifies an analog signal from said first node;

a first analog-digital converter that converts an analog signal from said first node into a digital signal;

a first digital-analog converter that converts the digital signal output from said first analog-digital converter into an analog signal; and

a first differential amplifier that amplifies the difference between the analog signal from said first operational amplifier and the analog signal output from said first digital-analog converter and outputs the amplified difference to said second node,

said control device controlling said selector so that after the input analog signal is applied to said first node, conversion operation by said first analog-digital converter, conversion operation by said first digital-analog converter, and amplifying operation by said first differential amplifier are carried out for a prescribed number of cycles.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2003
From: WADA, ATSUSHI; TANI, KUNIYUKI
To: SANYO ELECTRIC CO., LTD.
Reel/Frame 014466/0567 →
Priority Claims (1)
JP 2002-258058 · Sep 3, 2002 · national
Continuity (1)
Related Publication 20040041722A1 · Mar 4, 2004