IP Library Granted Patent US 6,897,101
Granted Patent B2
US 6,897,101 · App. 10/685,064 · Granted May 24, 2005

Method for writing to the magnetoresistive memory cells of an integrated magnetoresistive semiconductor memory

Assignee: Infineon Technologies AG
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Quick Facts
Patent No.
US 6,897,101
App. No.
10/685,064
Granted
May 24, 2005
Kind
B2
Abstract

An integrated magnetoresisitive semiconductor memory configuration has MRAM memory cells located at crossover points of selection lines that are embedded in different, mutually separate line planes. A read/write current can be impressed in respective selection lines for writing to each MRAM memory cell and for reading an information item written therein. In this magnetoresistive semiconductor memory configuration, selection lines that serve for reading a cell information item are in each case located in separate first and second line planes in direct contact with the memory cells. A third and a fourth line plane are spatially separated and electrically isolated from the first and second line planes and are occupied by write selection lines for writing a cell information item.

Claims (12)

1. A method for writing to magnetoresistive memory cells, which comprises:

providing an integrated magnetoresistive semiconductor memory configuration having MRAM memory cells located in a memory cell plane at crossover points between first selection lines embedded in a first line plane directly contacting the MRAM memory cells and second selection lines embedded in a second line plane directly contacting the MRAM memory cells, the second line plane being separate from the first line plane, the first selection lines and the second selection lines for impressing read/write currents for writing information items to the MRAM memory cells and for impressing read/write currents for reading the information items from the MRAM memory cells;

providing the integrated magnetoresistive semiconductor memory configuration with a third line plane being contiguous with one of the first and second line planes and electromagnetically associated with the MRAM memory cells in the memory call plane but spatially separated and electrically isolated from the first line plane and the second line plane;

providing the third line plane with write selection lines for writing a cell information item to the MRAM memory cells in the memory cell plane;

providing the integrated magnetoresistive semiconductor memory configuration with a fourth line plane being contiguous with the other one of the first and second line planes to which the third line plane is not contiguous and electromagnetically associated with the MRAM memory cells in the memory call plane but spatially separated and electrically isolated from the first line plane, the second line plane, and the third line plane;

providing the fourth line plane with write selection lines for writing a cell information item to the MRAM memory cells in the memory cell plane;

impressing a main write current in a direction through one of the write selection lines in the third line plane and through one of the write selection lines in the fourth line plane for writing to a particular one of the MRAM cells, while also impressing an additional write current through one of the first selection lines adjoining the particular one of MRAM memory cells and through one of the second selection lines adjoining the particular one of MRAM memory cells; and

when impressing the additional write current, impressing the additional write current being small compared to the main write current and in the same direction as the main write current in the write selection line in the respectively contiguous third and fourth line plane.

2. The method according to claim 1 , which further comprises:

when impressing the additional write current, setting a current intensity of the additional write current such that a maximum voltage drop is established along the one of the first selection lines adjoining the particular one of MRAM memory cells and along the one of the second selection lines adjoining the particular one of MRAM memory cells;

defining a current-voltage characteristic curve of the particular one of MRAM memory cells such that the current-voltage characteristic curve has a region of high resistance and a region of low resistance; and

ensuring that the maximum voltage drop lies in the region of high resistance in the current-voltage characteristic curve of the particular one of MRAM memory cells.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036723/0021 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023768/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2005
From: WEITZ, PETER
To: INFINEON TECHNOLOGIES AG
Reel/Frame 016444/0303 →
Priority Claims (1)
DE 101 18 197 · Apr 11, 2001 · national
Continuity (2)
Continuation PCTDE020125600 · Apr 5, 2002
Related Publication 20040087134A1 · May 6, 2004