Transistor sidewall spacer stress modulation
A semiconductor fabrication process and the resulting integrated circuit include forming a gate electrode ( 116 ) over a gate dielectric ( 104 ) over a semiconductor substrate ( 102 ). A spacer film ( 124 ) exhibiting a tensile stress characteristic is deposited over the gate electrode ( 116 ). The stress characteristics of at least a portion of the spacer film is then modulated ( 132, 192 ) and the spacer film ( 124 ) is etched to form sidewall spacers ( 160, 162 ) on the gate electrode sidewalls. The spacer film ( 124 ) is an LPCVD silicon nitride in one embodiment. Modulating ( 132 ) the spacer film ( 124 ) includes implanting Xenon or Germanium into the spacers ( 160 ) at an implant energy sufficient to break at least some of the silicon nitride bonds. The modulation implant ( 132 ) may be performed selectively or non-selectively either before or after etching the spacer film ( 124 ).
1. A semiconductor fabrication process, comprising:
forming a gate electrode over a gate dielectric over a semiconductor substrate;
thermally depositing, at a temperature in the range of approximately 550 to 750° C., a silicon nitride spacer film over the gate electrode, the deposited spacer film exhibiting a first tensile stress;
modulating a stress characteristic of at least a portion of the spacer film from the first tensile stress to a second tensile stress; and
etching the spacer film to form sidewall spacers laterally disposed on either side of the gate electrode, wherein at least a portion of the sidewall spacers include sidewall spacers exhibiting the second tensile stress.
2. The process of claim 1 , wherein modulating the stress characteristic comprises implanting a species into at least a portion of the spacer film.
3. A semiconductor fabrication process, comprising:
forming a gate electrode over a gate dielectric over a semiconductor substrate;
depositing a spacer film over the gate electrode, the deposited spacer film exhibiting a first tensile stress;
modulating a stress characteristic of at least a portion of the spacer film from the first tensile stress to a second tensile stress; and
etching the spacer film to form sidewall spacers laterally disposed on either side of the gate electrode, wherein at least a portion of the sidewall spacers include sidewall spacers exhibiting the second tensile stress;
wherein modulating the stress characteristic comprises implanting Xenon into at least a portion of the spacer film.
4. The process of claim 3 , wherein implanting Xenon further includes implanting Xenon into portions of the spacer film over p-channel transistors.
5. The process of claim 4 , wherein implanting Xenon still further includes implanting Xenon at an energy of at least 180 keV.
6. The process of claim 4 , wherein implanting Xenon still further includes implanting at an implant angle of approximately 45°.
7. The process of claim 2 , wherein the ion implanting includes implanting Germanium into the spacer film.
8. The process of claim 7 , wherein implanting Germanium further includes implanting Germanium at an energy of at least 80 keV and an implant angle of approximately 10°.
9. A semiconductor fabrication process, comprising:
depositing a silicon nitride spacer film exhibiting a first tensile stress characteristic over a gate electrode and a semiconductor substrate over which the gate electrode is positioned;
etching the spacer film to form silicon nitride spacers on sidewalls of the gate electrode; and
implanting at least some of the sidewall spacers with an implant species selected from Xenon and Germanium using an implant angle of 10° or greater to modulate a stress characteristic of the implanted spacers.
10. The process of claim 9 , wherein depositing silicon nitride still further includes depositing silicon nitride with a thermal CVD process in which the deposition temperature is in the range of approximately 550 to 750° C.
11. The process of claim 9 , wherein implanting at least some of the sidewall spacers still further includes implanting with an implant energy not less than 80 keV.
12. A semiconductor fabrication process, comprising:
depositing a silicon nitride spacer film exhibiting a first tensile stress characteristic over a gate electrode and a semiconductor substrate over which the gate electrode is positioned;
etching the spacer film to form silicon nitride spacers on sidewalls of the gate electrode; and
selectively implanting at least some of the sidewall spacers of n-channel transistors with an Xenon ions at an implant energy of approximately 180 keV and an implant angle of approximately 45° C. to modulate a stress characteristic of the implanted spacers.
13. A semiconductor fabrication process, comprising:
depositing a silicon nitride spacer film over a gate electrode and a semiconductor substrate over which the gate electrode is positioned;
etching the spacer film to form silicon nitride spacers on sidewalls of the gate electrode; and
blanket implanting at least some of the sidewall spacers with Germanium at an implant energy of 80 keV and an implant angle of approximately 10° to modulate a stress characteristic of the implanted spacers.