Fractional N synthesizer with reduced fractionalization spurs
A fractional N synthesizer is disclosed. The synthesizer includes a phase detector that receives first and second input signals and generates a pulse width modulated (PWM) output signal having a pulse width indicative of the phase relationship between the input signals. A pulse-width-to-amplitude (PW/A) conversion circuit connected to a loop filter where the conversion circuit receives the phase detector output signal and generates a PW/A output signal having an amplitude indicative of the phase detector output signal pulse width. The phase detector output signal may comprise a periodic series of pulses having varying pulse widths and the PW/A output signal amplitude changes at the end of each pulse to reflect the corresponding pulse width. The conversion circuit may include a current circuit connected to a capacitor, where the current signal receives the phase detector output and sources a constant current during a charging phase of the phase detector output signal.
1. A fractional N synthesizer, comprising:
a phase detector configured to receive first and second input signals and further configured to generate a phase detector output signal having a pulse width indicative of the phase relationship between the first and second input signals;
a pulse-width-to-amplitude (PW/A) conversion circuit configured to receive the phase detector output signal and enabled to generated a PW/A output signal having an amplitude indicative of the phase detector output signal pulse;
a loop filter configured to low pass filter the PW/A output signal to generate a loop filter output having voltage;
a voltage controlled oscillator (VCO) configured to receive the loop filter output and further configured to generate an RF output signal having a frequency determined by the loop filter output signal voltage;
a fractional N divider circuit configured to receive the VCO output signal and further configured to generate a digital signal having a frequency that is a fraction of the VCO output signal frequency, wherein the fraction is determined by a programmable divider circuit modulus;
an accumulator circuit configured to receive the fractional N divider circuit output signal and enabled to alter the programmable divider circuit modulus;
wherein the PW/A conversion circuit includes a current circuit connected to a capacitor, wherein the current circuit is configured to receive the phase detector output signal as an input and further configured to source a constant current during a charging phase, wherein each charging phase lasts for the duration of the phase detector output signal; and
wherein the current circuit is further configured to sink a current during a discharge phase, wherein the sink current is sufficient to discharge the capacitor to a predetermined clamp voltage prior to the start of the next successive charging phase.
2. The system of claim 1 , wherein the output of a constant frequency oscillator comprises the first phase detector input signal.
3. The system of claim 2 , wherein the output of the fractional N divider circuit comprises the second phase detector input signal.
4. The system of claim 1 , wherein the phase detector output signal comprises a periodic series of pulses having varying pulse widths and wherein the amplitude of the PW/A conversion circuit output signal changes at temporally uniform intervals.
5. The system of claim 4 , wherein the PW/A output signal amplitude changes at the end of each pulse to reflect the corresponding pulse width.
6. A fractional N synthesizer, comprising:
a phase detector configured to receive first and second input signals and further configured to generate a phase detector output signal having a pulse width indicative of the phase relationship between the first and second input signals;
a pulse-width-to-amplitude (PW/A) conversion circuit configured to receive the phase detector output signal and enabled to generate a PW/A output signal having an amplitude indicative of the phase detector output signal pulse;
a loop filter configured to low pass filter the PW/A output signal to generate a loop filter output having voltage;
a voltage controlled oscillator (VCO) configured to receive the loop filter output and further configured to generate an RF output signal having a frequency determined by the loop filter output signal voltage;
a fractional N divider circuit configured to receive the VCO output signal and further configured to generate a digital signal having a frequency that is a fraction of the VCO output signal frequency, wherein the fraction is determined by a programmable divider circuit modulus;
an accumulator circuit configured to receive the fractional N divider circuit output signal and enabled to alter the programmable divider circuit modulus;
wherein the PW/A conversion circuit includes a current circuit connected to a capacitor having voltage, wherein the current circuit is configured to receive the phase detector output signal as an input and further configured to source a constant current during a charging phase, wherein each charging phase lasts for the duration of the phase detector output signal;
wherein the capacitor voltage provides a sample input to a sample-and-hold (S/H) circuit; and
wherein the first input signal provides a trigger input to the S/H circuit.