Method for creating neo-wafers from singulated integrated circuit die and a device made according to the method
A neo-wafer made from integrated circuit die and methods for making a neo-wafer are disclosed. Recesses are formed on a substrate and a dielectric layer with conductive pads is created for the receiving of one or more die. Die are flip-chip bonded to the conductive pads and all voids under-filled. The neo-wafer is thinned to expose the dielectric and the conductive pads exposed, creating a neo-wafer.
1. A method for creating a neo-wafer comprising: providing a first layer with an upper surface and a lower surface, forming at least one dielectric structure on said upper surface, forming at least one conductive pad on said at least one dielectric structure, providing a second layer and a third layer, bonding said second layer to said third layer with a first adhesive, removing a predetermined portion of said third layer so as to expose a predetermined portion of said first adhesive, removing said exposed predetermined portion of said first adhesive, removing a predetermined portion of said second layer to form at least one sidewall structure with an uppermost surface, bonding said uppermost sidewall surface to said upper surface of said first layer with a second adhesive whereby said at least one dielectric structure is disposed within said at least one sidewall structure to form at least one recess, removing the remaining portion of said third layer, removing the remaining portion of said first adhesive, disposing an integrated circuit die within said at least one recess, said integrated circuit die having at least one I/O pad, and forming an electrical interconnection between said conductive pad and said at least one I/O pad.
2. The method according to claim 1 comprised of the further step of substantially filling the volume between said die and said at least one recess with an under-fill material.
3. The method according to claim 2 comprised of the further step of removing a predetermined portion of said upper surface whereby said upper surface is planarized.
4. The method according to claim 3 comprised of the further step of removing a predetermined portion of said lower surface whereby said dielectric layer is exposed.
5. The method according to claim 4 comprised of the further step of forming at least one via in said dielectric layer so as to expose said at least one conductive pad.
6. The method according to claim 5 wherein said at least one I/O pad includes a solder ball disposed thereon.