Memory cell and method for forming the same
A semiconductor memory cell structure having 4F 2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.
1. A plurality of memory cells formed on a surface of a substrate, comprising:
an active region formed in the substrate;
a plurality of posts formed on the surface of the substrate over the active region, the plurality of posts formed from a semiconductor material and spaced apart from one another by respective regions;
a plurality of contacts formed over and electrically coupled to the active region, each contact having at least a portion formed adjacent a respective one of the regions for a pair of posts;
a plurality of memory cell capacitors formed on a respective one of the plurality of posts; and
a plurality of gate structures formed adjacent a respective one of the plurality of posts to provide a respective vertical transistor configured to electrically couple the respective memory cell capacitor to the active region.
2. The plurality of memory cells of claim 1 wherein each contact of the plurality of contacts is formed over a respective portion of the active region that extends laterally on the surface of the substrate from a respective region between a pair of posts.
3. The plurality of memory cells of claim 1 wherein each contact of the plurality of contacts is formed adjacent a respective one of the regions for the pair of posts and equidistant from each of the posts of the pair.
4. The plurality of memory cells of claim 1 wherein each contact of the plurality of contacts comprises a contact having a first portion formed adjacent a respective one of the regions for a pair of posts and further having a second portion formed in the region between the pair of posts.
5. The plurality of memory cells of claim 1 wherein the active region formed in the substrate comprises an active region extending laterally across the surface of the substrate and the plurality of posts formed over the active region comprises at least three posts.
6. The plurality of memory cells of claim 1 wherein each post of the plurality of posts comprises a post formed from a doped epitaxial silicon material.
7. The plurality of memory cells of claim 1 wherein each post of the plurality of posts comprises a post having first and second opposite lateral surfaces and each gate structure of the plurality of gate structures is formed adjacent to the first and second opposite lateral surfaces of the respective post.
8. The plurality of memory cells of claim 1 wherein each post of the plurality of posts comprises a post having first and second adjacent lateral surfaces and each gate structure of the plurality of gate structures is formed adjacent to the first and second adjacent lateral surfaces of the respective post.
9. The plurality of memory cells of claim 1 wherein each memory cell capacitor of the plurality of memory cell capacitors comprises a container-shaped capacitor structure.
10. A memory cell structure formed on a substrate having a surface, comprising:
an active region formed in the substrate;
a semiconductor post formed on the active region;
first and second contacts formed on the active region and on laterally disposed on opposite sides of the semiconductor post along the surface of the substrate;
a memory cell capacitor formed on the semiconductor post; and
a vertical access transistor having a gate formed adjacent the semiconductor post and configured to electrically couple the capacitor to the first and second contacts in response to being activated.
11. The memory cell structure of claim 10 wherein the first and second contacts are formed equidistant from the semiconductor post.
12. The memory cell structure of claim 10 wherein the first and second contacts are formed from a titanium material.
13. The memory cell structure of claim 10 wherein the first and second contacts are formed from a tungsten material.
14. The memory cell structure of claim 10 wherein the first and second contacts are formed from a metal material.
15. The memory cell structure of claim 10 wherein the memory cell capacitor comprises:
a first capacitor plate layer formed from a first material;
a second capacitor plate layer formed from a second material; and
a dielectric layer disposed between the first and second capacitor plate layers.
16. The memory cell structure of claim 15 wherein the dielectric layer comprises a layer of aluminum oxide.
17. The memory cell structure of claim 15 wherein the dielectric layer comprises a layer of hafnium oxide.
18. The memory cell structure of claim 15 wherein the first and second plates are formed from the same material.
19. The memory cell structure of claim 15 wherein the first and second plates are formed from a titanium material.
20. The memory cell structure of claim 15 wherein the first and second plates are formed from a tantalum material.
21. The memory cell structure of claim 15 wherein the first and second plates are formed from a platinum material.
22. The memory cell structure of claim 10 wherein the gate of the vertical access transistor is formed from a titanium material.
23. The memory cell structure of claim 10 wherein the gate of the vertical access transistor is formed from a molybdenum material.
24. The memory cell structure of claim 10 wherein the gate of the vertical access transistor is formed from a nickel material.
25. The memory cell structure of claim 10 wherein the gate of the vertical access transistor is formed from a silicon material.