Integrated dual damascene RIE process with organic patterning layer
View Patent ↗A dual damascene conductor structure is formed on a substrate with an exposed conductor on top covered by a buried cap, a dielectric layer (DL) and an organic layer (OL). Form a lower via hard mask layers over the OL and form a top trench patterning hard mask over the lower, via hard mask. Form a trench pattern hole through the trench hard mask layer; and form a via pattern hole through the via hard mask layer in a region exposed below the trench pattern hole. Etch a via pattern hole into the OL and then etch a via pattern hole down into the DL. Etch away the trench pattern layer and the OL layer below the trench pattern hole. Etch the via hole through the DL exposing the cap while simultaneously partially etching the DL to a final trench depth to form a trench in the DL below the trench pattern hole, with the trench having a bottom above the cap and sidewalls in the DL.
1. A method of forming a dual damascene conductor structure comprising:
providing a substrate having a top surface with an electrical conductor exposed on said top surface;
forming a cap layer having a bottom surface located above said top surface of said substrate;
forming a dielectric layer having a bottom surface located above said cap layer;
forming an organic (OL) layer over said dielectric layer;
forming a lower, via hard mask layer and a tap, trench hard mask layer over said OL layer;
forming a trench patterning hole through said top, trench hard mask layer;
forming a via patterning hole through said lower, via hard mask layer inside said trench patterning hole through said top, trench hard mask layer;
etching said via patterning hole through said organic layer and then etching said via patterning hole into said dielectric layer;
etching away said via hard mask layer below said trench patterning hole and then etching away said OL layer below said trench patterning hole;
etching said via hole through said bottom of said dielectric layer to said cap layer while partially etching a trench into said dielectric layer below said trench patterning hole with said trench having a bottom and sidewalls in said dielectric layer with said bottom being spaced above said cap layer; and
etching through said cap layer below said via hole to expose said conductor.
2. The method of claim 1 wherein a buried cap layer is formed between said substrate and said dielectric layer.
3. The method of claim 1 wherein a glass layer is formed over said OL layer.
4. The method of claim 1 wherein said dielectric layer is a low k Inter-Layer Dielectric (ILD) layer.
5. The method of claim 1 wherein said OL layer comprises an organic polymer with thermal stability to 400° C. or greater and said OL layer is etchable by a radio frequency (RF) plasma process using H 2 /N 2 , O 2 /N 2 , H 2 /Ar, or O 2 /Ar.
6. The method of claim 1 wherein:
a buried cap layer is formed between said substrate and said dielectric layer; and
a glass layer is formed over said OL layer.
7. The method of claim 1 wherein:
a buried cap layer is formed between said substrate and said dielectric layer;
a glass layer is formed over said OL layer; and
said dielectric layer is a low k Inter-Layer Dielectric (ILD) layer.
8. The method of claim 1 wherein:
said OL layer comprises an organic polymer with thermal stability to 400° C. or greater and said OL layer is etchable by a radio frequency (RF) plasma process using H 2 /N 2 , O 2 /N 2 , H 2 /Ar, or O 2 /Ar;
said buried cap layer is formed between said substrate and said dielectric layer;
a glass layer is formed over said OL layer; and
said dielectric layer is a low k Inter-Layer Dielectric (ILD) layer.
9. The method of claim 1 wherein said trench is etched to a Final Trench Depth line (FTD) in said dielectric layer.
10. The method of claim 1 wherein:
said OL layer comprises an organic polymer with thermal stability to 400° C or greater and said OL layer is etchable by a radio frequency (RF) plasma process using H 2 /N 2 , O 2 /N 2 , H 2 /Ar, or O 2 /Ar;
said buried cap layer is formed between said substrate and said dielectric layer;
a glass layer is formed over said OL layer;
said dielectric layer is a low k Inter-Layer Dielectric (ILD) layer; and
said trench is etched to a Final Trench Depth line (FTD) in said dielectric layer.
11. A method of forming a dual damascene conductor structure comprising:
providing a substrate having a top surface with an electrical conductor exposed on said top surface, with a buried cap layer covering said top surface and said conductor; and forming a dielectric layer having a bottom surface located above said top surface of said substrate;
forming a glass layer over said dielectric layer and forming an organic (OL) layer over said glass layer;
forming a via hard mask layer over said organic layer;
forming a trench patterning hard mask layer over said via hard mask layer;
forming a trench patterning hole through said trench patterning hard mask layer exposing portions of said via hard mask layer;
forming a via patterning hole through said via hard mask layer exposed through trench patterning hole through said trench patterning hard mask layer;
etching through said via patterning hole to etch a via hole through said organic (OL) layer and then etching through said via patterning hole to etch said via hole into said dielectric layer;
etching away said via hard mask layer below said trench patterning hole and then etching away exposed portions of said organic(OL) layer below said trench patterning hole;
etching said via hole through said bottom of said dielectric layer exposing said cap layer while partially etching a trench into said dielectric layer below said trench patterning hole with said trench having sidewalls and a bottom in said dielectric layer, with said bottom being at a final trench depth spaced above said cap layer;
etching through said cap layer below said via hole to expose said conductor; and
forming a dielectric liner layer on sidewalls of said trench and forming a conductor inside said sidewalls in said trench.
12. The method of claim 11 wherein said dielectric layer is a low k Inter-Layer Dielectric (ILD) layer.
13. The method of claim 11 wherein said CL layer comprises an organic polymer with thermal stability to 400° C. or greater and said OL layer is etchable by a radio frequency (RF) plasma process using H 2 /N 2 , O 2 /N 2 , H 2 /Ar, or O 2 /Ar.
14. The method of claim 11 wherein said trench is etched to a Final Trench Depth line (FTD) in said dielectric layer.
15. The method of claim 11 wherein:
said OL layer comprises an organic polymer with thermal stability to 400° C. or greater;
said OL layer is etchable by a radio frequency (RF) plasma process using H 2 /N 2 , O 2 /N 2 , H 2 /Ar, or O 2 /Ar; and
said trench is etched to a Final Trench Depth line (FTD) in said dielectric layer.
16. The method of claim 11 wherein an ARC layer is formed below a photoresist layer when patterning said via hard mask layer and said trench patterning hard mask layer.
17. The method of claim 11 wherein:
said dielectric layer is a low k Inter-Layer Dielectric (ILD) layer; and
said OL layer comprises an organic polymer with thermal stability to 400° C. or greater; and
said OL layer is etchable by a radio frequency (RF) plasma process using H 2 /N 2 , O 2 /N 2 , H 2 /Ar, or O 2 /Ar.
18. The method of claim 11 wherein:
said dielectric layer is a low k Inter-Layer Dielectric (ILD) layer;
said OL layer comprises an organic polymer with thermal stability to 400° C. or greater;
said OL layer is etchable by radio frequency (RF) plasma process using H 2 /N 2 , O 2 /N 2 , H 2 /Ar, or O 2 /Ar; and
said trench is etched to a Final Trench Depth line (FTD) in said dielectric layer.
19. The method of claim 11 wherein:
said dielectric layer is a low k Inter-Layer Dielectric (ILD) layer;
said OL layer comprises an organic polymer with thermal stability to 400° C. or greater;
said OL layer is etchable by a radio frequency (RF) plasma process using H 2 /N 2 , O 2 /N 2 , H 2 /Ar, or O 2 /Ar; and
said trench is etched to a Final Trench Depth line (FTD) in said dielectric layer.
20. The method of claim 11 wherein:
an ARC layer is formed below a photoresist layer when patterning said via hard mask layer and said trench patterning hard mask layer; and
said ARC layer and said trench patterning hard mask layer are removed prior to etching said trench in said dielectric layer.