Substrate engineering for optimum CMOS device performance
View Patent ↗An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has a (110) surface orientation and a notch pointing in a <001> direction of current flow; and at least one PFET and at least one NFET located on the semiconductor substrate. The at least one PFET has a current flow in a <110> direction and the at least one NFET has a current flow in a <100> direction. The <110> direction is perpendicular to the <100> direction. A method of fabricating such as integrated semiconductor structure is also provided.
1. An integrated semiconductor structure comprising a semiconductor substrate comprising a Group IV semiconducting material that has a (110) surface orientation and a notch pointing in a <001> direction of current flow; and
at least one PFET and at least one NFET located on the semiconductor substrate, said at least one PFET and said at least one NFET each having a device channel parallel to a surface of said semiconducting substrate, wherein said at least one PFET has a current flow in a <110> direction and the at least one NFET has a current flow in a <100> direction, said <110> direction is perpendicular to the <100> direction, and wherein the at least one PFET and the at least one NFET each include source/drain regions, wherein the source/drain regions of the at least one PFET lie perpendicular to the source/drains of the at least one NFET.
2. The integrated semiconductor structure of claim 1 wherein said Group IV semiconducting material is selected from the group consisting of Si, SiGe, SiC, and SiGeC.
3. The integrated semiconductor structure of claim 2 wherein said Group IV semiconducting material is Si.
4. An integrated semiconductor structure comprising
a semiconductor substrate comprising a Group IV semiconducting material that has a (110) surface orientation and a notch pointing in a <001> direction of current flow; and
at least one PFET and at least one NFET located on the semiconductor substrate, said at least one PFET and said at least one NFET each having a device channel parallel to a surface of said semiconducting substrate, wherein said at least one PFET has a current flow in a <110> direction and the at least one NFET has a current flow in a <100> direction, said <110> direction is perpendicular to the <100> direction, and wherein the at least one NFET and the at least one PFET each comprise a gate dielectric located on the semiconductor substrate, a patterned gate conductor located on portions of the gate dielectric, and spacers located on exposed sidewalls of the patterned gate conductor.
5. The integrated semiconductor structure of claim 4 wherein the gate dielectric is an oxide.
6. The integrated semiconductor structure of claim 4 wherein the patterned gate conductor comprises polySi.
7. The integrated semiconductor structure of claim 4 wherein the at least one PFET and the at least one NFET each include source/drain regions, wherein the source/drain regions of the at least one PFET lie perpendicular to the source/drain of the at least one NFET.