Methods for forming strained-semiconductor-on-insulator device structures by use of cleave planes

1. A method for forming a structure, the method comprising:

forming a first strained semiconductor layer over a first substrate to define a layer structure, the layer structure comprising a porous layer defining a cleave plane;

forming a first relaxed layer over the first substrate;

planarizing the first relaxed layer;

forming a second relaxed layer over the first relaxed layer after the first relaxed layer is planarized;

bonding the first strained semiconductor layer to an insulator layer disposed on a second substrate; and

removing the first substrate from the first strained semiconductor layer by cleaving at the cleave plane, the strained semiconductor layer remaining bonded to the insulator layer,

wherein the first relaxed layer includes the porous layer defining a cleave plane; and the first strained semiconductor layer is formed over the first and second relaxed layers.

2. The method of claim 1 , wherein planarizing comprises chemical-mechanical polishing.

3. The method of claim 1 , wherein the relaxed layer comprises SiGe.

4. A method for forming a structure, the method comprising:

forming a first strained semiconductor layer over a first substrate to define a layer structure, the layer structure comprising a porous layer defining a cleave plane;

bonding the first strained semiconductor layer to an insulator layer disposed on a second substrate; and

removing the first substrate from the first strained semiconductor layer by cleaving at the cleave plane, the strained semiconductor layer remaining bonded to the insulator layer and at least a portion of the porous layer remaining disposed over the first strained semiconductor layer after cleaving; and

removing the portion of the porous layer after cleaving,

wherein removing the portion of the porous layer comprises thermal oxidation.

5. A method for forming a structure, the method comprising:

forming a first relaxed layer over a first substrate;

thereafter forming a porous layer by forming a plurality of pores in the first relaxed layer to define a cleave plane;

forming a first strained semiconductor layer over the first substrate and the first relaxed layer to define a layer structure;

bonding the first strained semiconductor layer to an insulator layer disposed on a second substrate; and

removing the first substrate from the first strained semiconductor layer by cleaving at the cleave plane, the strained semiconductor layer remaining bonded to the insulator layer.

6. The method of claim 5 , wherein the porous layer is disposed at a top portion of the first relaxed layer.

7. The method of claim 5 , further comprising:

forming a second relaxed layer over the first relaxed layer,

wherein the strained semiconductor layer is formed over the second relaxed layer.

8. The method of claim 5 , wherein at least a portion of the porous layer remains disposed over the first strained semiconductor layer after cleaving.

9. The method of claim 8 , further comprising:

removing the portion of the porous layer after cleaving.

10. The method of claim 9 , wherein removing the portion of the porous layer comprises cleaning with a wet chemical solution.

11. The method of claim 10 , wherein the wet chemical solution comprises hydrogen peroxide.

12. The method of claim 10 , wherein the wet chemical solution comprises hydrofluoric acid.

13. The method of claim 5 , further comprising forming a dielectric layer above the first strained semiconductor layer prior to bonding.

14. The method of claim 5 , wherein the porous layer is formed by electrochemical etching.

15. The method of claim 5 , further comprising:

defining a transistor over the second substrate, the transistor including a gate disposed above the first strained semiconductor layer,

wherein the gate comprises a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound.

16. The method of claim 5 , wherein the relaxed layer comprises SiGe.