IP Library Granted Patent US 7,327,786
Granted Patent B2
US 7,327,786 · App. 10/452,262 · Granted Feb 5, 2008

Method for improving rate-distortion performance of a video compression system through parallel coefficient cancellation in the transform

Assignee: LSI Logic Corporation
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Quick Facts
Patent No.
US 7,327,786
App. No.
10/452,262
Granted
Feb 5, 2008
Kind
B2
Abstract

A method for improving rate distortion performance of a compression system through parallel coefficient cancellation in a transform comprising the steps of (A) determining a block sum of absolute values for each of a plurality of blocks in a macroblock and (B) setting one or more coefficient values of a block to zero in response to a block sum value of said block being less than a first predetermined threshold value.

Claims (38)

1. A method for improving rate distortion performance of a compression system through parallel coefficient cancellation in a transform comprising the steps of:

(A) generating quantized coefficient values for each of a plurality of blocks in a macroblock;

(B) determining a block sum value for each of the plurality of blocks in said macroblock using a sum of absolute values (SAV) of respective quantized coefficient values for each of the plurality of blocks; and

(C) setting one or more of the quantized coefficient values of a block to zero in response to the block sum value of said block being less than a first predetermined threshold value.

2. The method according to claim 1 , further comprising the steps of:

determining a group of blocks sum of absolute values of the quantized coefficient values for one or more groups of one or more of said plurality of blocks in said macroblock; and

setting the quantized coefficient values for said one or more groups of blocks to zero in response to a corresponding group of blocks sum value being less than a second predetermined threshold value.

3. The method according to claim 1 , further comprising the steps of:

determining a block sum of absolute values of the quantized coefficient values for said macroblock; and

setting the quantized coefficient values of said macroblock to zero in response to said block sum of absolute values for said macroblock being less than a third predetermined threshold value.

4. The method according to claim 1 , wherein said absolute values are calculated during quantization of said plurality of blocks.

5. The method according to claim 1 , wherein said first threshold value is determined based on a class of said block and a type of said macroblock.

6. The method according to claim 2 , wherein said second threshold value is determined based on a class of said group of blocks and a type of said macroblock.

7. The method according to claim 3 , wherein said third threshold value is determined based on a type of said macroblock.

8. The method according to claim 1 , wherein determining said block sum of absolute values comprises performing a weighted programmable sum of absolute values calculation.

9. The method according to claim 1 , wherein the block sum of absolute values for each of the plurality of blocks are determined in parallel.

10. The method according to claim 1 , wherein determining said block sum of absolute values for each of the plurality of blocks in said macroblock comprises:

determining a block sum of absolute values for each luma block based on a sum of twice the value of each quantized coefficient absolute value, except for the DC frequency coefficient and triple the value of intra-block only coefficient; and

determining a block sum of absolute values for each chroma block based on a sum of twice the value of each quantized coefficient absolute value.

11. An apparatus comprising:

a first circuit configured to present quantized coefficients for a plurality of blocks in a macroblock; and

a second circuit configured to calculate a block sum of absolute values for each of said plurality of blocks in response to said quantized coefficients, wherein said second circuit is further configured to set one or more of said guantized coefficients of a block to zero in response to a corresponding block sum of absolute values of said block having a value less than a first predetermined threshold value.

12. The apparatus according to claim 11 , wherein said second circuit is further configured to set the quantized coefficients of a group of one or more of said plurality of blocks to zero in response to a block sum of absolute values of the quantized coefficients for said group of blocks having a value less than a second predetermined threshold value.

13. The apparatus according to claim 12 , wherein said second circuit is further configured to set all quantized coefficients of a macroblock to zero in response to a block sum of absolute values of the quantized coefficients for said macroblock having a value less than a third predetermined threshold value.

14. The apparatus according to claim 11 , wherein said apparatus comprises an encoder.

15. The apparatus according to claim 11 , wherein said apparatus comprises a transcoder.

16. The apparatus according to claim 11 , wherein said apparatus comprises a transcoding statmux system of a video transmission system.

17. The apparatus according to claim 11 , wherein said second circuit is further configured to:

set one or more of said quantized coefficients of a block to zero in response to a corresponding block sum of absolute values of said quantized coefficients for said block having a value less than a first predetermined threshold value;

set the quantized coefficients of a group of one or more of said plurality of blocks to zero in response to a block sum of absolute values of said quantized coefficients for said group of blocks having a value less than a second predetermined threshold value; and

set all quantized coefficients of a macroblock to zero in response to a block sum of absolute values of said quantized coefficients for said macroblock having a value less than a third predetermined threshold value.

18. The apparatus according to claim 17 , wherein said first threshold value is smaller than said second threshold value.

19. The apparatus according to claim 17 , wherein said second threshold value is smaller than said third threshold value.

20. The apparatus according to claim 17 , wherein said first threshold value is smaller than said second threshold value and said second threshold value is smaller than said third threshold value.

21. The apparatus according to claim 11 , further comprising a zig-zag scan serialization circuit coupled to said second circuit.

22. An apparatus comprising:

means for presenting quantized coefficients for a plurality of blocks in a macroblock; and

means for determining a block sum of absolute values for each of said plurality of blocks in response to said quantized coefficients, wherein respective quantized coefficients of each of said plurality of blocks are set to zero in response to said block sum of absolute values for each of said plurality of blocks and one or more predetermined threshold values.

Assignments (10)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER PREVIOUSLY RECORDED AT REEL: 047357 FRAME: 0302. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048674/0834 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED ON REEL 047195 FRAME 0658. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047357/0302 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0658 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2003
From: WINGER, LOWELL L.; NOVOTNY, PAVEL; COTE, GUY
To: LSI LOGIC CORPORATION
Reel/Frame 014150/0661 →
Continuity (1)
Related Publication 20040240556A1 · Dec 2, 2004