IP Library › Granted Patent US 7,340,352
Granted Patent B2
US 7,340,352 · App. 11/588,319 · Granted Mar 4, 2008

Inspecting method, inspecting apparatus, and method of manufacturing semiconductor device

Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 7,340,352
App. No.
11/588,319
Granted
Mar 4, 2008
Kind
B2
Abstract

An inspecting method is capable of efficiently inspecting a wafer. According to the inspecting method, the chip area of a wafer is inspected for defects, and based on the results, a defect density D 0p of each of peripheral-zone chips in the chip area which are located closely to the peripheral area of the wafer is calculated. A peripheral-zone chip with a high defect density D 0p is selected, and an area in the peripheral area which is outward of the selected peripheral-zone chip is inspected for defects. Since only the area in the peripheral area which is located outward of the peripheral-zone chip selected based on the defect density D 0p is inspected for defects, the wafer is inspected efficiently.

Claims (45)

1. A method of inspecting a wafer for defects, the wafer having a chip area and a peripheral area outward of said chip area, said method comprising the steps of:

(a) performing a first defect inspection on said chip area;

(b) calculating defect densities of peripheral-zone chips in said chip area which are close to said peripheral area, based on said first defect inspection;

(c) selecting one of said peripheral-zone chips based on the calculated defect density; and

(d) performing a second defect inspection on an area in said peripheral area which is positioned outward of the selected peripheral-zone chip.

2. The method according to claim 1 , wherein said step (c) comprises the step of:

selecting one of peripheral-zone chips whose defect density is greater than a predetermined value.

3. The method according to claim 1 , further comprising the steps of:

after said step (a) and before said step (b), calculating an overall defect density of said chip area based on said first defect inspection; and

wherein said step (c) comprises the step of:

selecting one of peripheral-zone chips whose defect density is greater than the calculated overall defect density of said chip area.

4. The method according to claim 1 , wherein said step (d) comprises the steps of:

establishing an inspection area of a predetermined shape in said peripheral area which is positioned outward of the selected peripheral-zone chip; and

performing said second defect inspection on said inspection area.

5. The method according to claim 4 , wherein said inspection area comprises a sectorial or arcuate area including an arcuate edge as a portion of an outer circumferential edge of said wafer.

6. The method according to claim 4 , wherein said inspection area comprises a hypothetical chip disposed in said peripheral area of said wafer.

7. An apparatus for inspecting a wafer for defects, the wafer having a chip area and a peripheral area outward of said chip area, said apparatus comprising:

first inspecting means for performing a first defect inspection on said chip area;

calculating means for calculating defect densities of peripheral-zone chips in said chip area which are close to said peripheral area, based on said first defect inspection;

selecting means for selecting one of said peripheral-zone chips based on the calculated defect density; and

second inspecting means for performing a second defect inspection on an area in said peripheral area which is positioned outward of the selected peripheral-zone chip.

8. The apparatus according to claim 7 , wherein said selecting means selects one of peripheral-zone chips whose defect density is greater than a predetermined value.

9. The apparatus according to claim 7 , further comprising:

means for an overall defect density of said chip area based on said first defect inspection; and

wherein said selecting means selects one of peripheral-zone chips whose defect density is greater than the calculated overall defect density of said chip area.

10. The apparatus according to claim 7 , wherein said second inspecting means establishes an inspection area of a predetermined shape in said peripheral area which is positioned outward of the selected peripheral-zone chip, and performs said second defect inspection on said inspection area.

11. The apparatus according to claim 10 , wherein said inspection area comprises a sectorial or arcuate area including an arcuate edge as a portion of an outer circumferential edge of said wafer.

12. An apparatus according to claim 10 , wherein said inspection area comprises a hypothetical chip disposed in said peripheral area of said wafer.

13. A method of manufacturing a semiconductor device from a wafer having a chip area and a peripheral area outward of said chip area, said method comprising the steps of:

(a) performing a first defect inspection on said chip area;

(b) calculating defect densities of peripheral-zone chips in said chip area which are close to said peripheral area, based on said first defect inspection;

(c) selecting one of said peripheral-zone chips based on the calculated defect density; and

(d) performing a second defect inspection on an area in said peripheral area which is positioned outward of the selected peripheral-zone chip.

14. The method according to claim 13 , said step (d) comprises the steps of:

establishing an inspection area of a predetermined shape in said peripheral area which is positioned outward of the selected peripheral-zone chip; and

performing said second defect inspection on said inspection area.

15. The method according to claim 14 , wherein said inspection area comprises a sectorial or arcuate area including an arcuate edge as a portion of an outer circumferential edge of said wafer.

16. The method according to claim 14 , wherein said inspection area comprises a hypothetical chip disposed in said peripheral area of said wafer.

17. The method according to claim 13 , further comprising the steps of:

(e) after said step (d), performing a necessary action on a process by which said wafer has been processed prior to said step (a); and

(f) performing a third defect inspection on the chip area and the peripheral area outward of said chip area of a next wafer which has been processed by said process on which said necessary action has been performed.

18. The method according to claim 17 , further comprising the steps of:

after said step (f), if the stability of said process is confirmed based on said third defect inspection, performing a fourth defect inspection on the chip area of a further next wafer which has been processed by said process subsequently to said next wafer;

calculating a defect density of a peripheral-zone chip which is located closely to the peripheral area outward of said chip area of said further next wafer, among chips in said chip area of said further next wafer, based on said fourth defect inspection; and

performing a fifth defect inspection on the peripheral area of said further next area only if the calculated defect density of the peripheral-zone chip on said further next wafer is greater than a predetermined value.

Assignments (4)
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021976/0089 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2006
From: TAKAHASHI, NAOHIRO; IRINO, KIYOSHI
To: FUJITSU LIMITED
Reel/Frame 018470/0618 →
Priority Claims (1)
JP 2006-123545 · Apr 27, 2006 · national
Continuity (1)
Related Publication 20070255513A1 · Nov 1, 2007