Semiconductor device

1. A semiconductor device comprising

first capacitance means and second capacitance means having different ON- and OFF-state capacitances, for bringing said first capacitance means or said second capacitance means from an ON- state into an OFF- state in a process of changing the potential of a first electrode of said first capacitance means and the potential of a first electrode of said second capacitance means from a first potential to a second potential thereby enlarging the difference between a potential input in a second electrode of said first capacitance means and a potential input in a second electrode of said second capacitance means and comparing said potential input in said second electrode of said first capacitance means and said potential input in said second electrode of said second capacitance means with each other.

2. The semiconductor device according to claim 1 , wherein

said first capacitance means and said second capacitance means having said different ON- and OFF- state capacitances include either transistor elements serving as capacitors or capacitive elements, switchable between ON- and OFF- states, other than said transistor elements.

3. The semiconductor device according to claim 1 , wherein

said first capacitance means and said second capacitance means have substantially identical threshold voltages bringing ON- states when said first electrode of said first capacitance means and said first electrode of said second capacitance means are at said first potential while bringing OFF- states when said first electrode of said first capacitance means and said first electrode of second capacitance means are at said second potential,

the potential of said first electrode of said first capacitance means and the potential of said first electrode of said second capacitance means are changed from said first potential to said second potential at a first rate of change thereby the potential of said second electrode of said first capacitance means and the potential of said second electrode of said second capacitance means are changed at a second rate of change smaller than said first rate of change.

4. The semiconductor device according to claim 3 , reducing said second rate of change for the potential of said second electrode of said first capacitance means by changing the potential of said first electrode of said first capacitance means and the potential of said first electrode of said second capacitance means at said first electrode of said second capacitance means at said first rate of change while reducing the absolute value of the difference between the potential of said second electrode of said first capacitance means and the potential of said first electrode of said first capacitance means below the absolute value of said threshold voltage of said first capacitance means thereby bringing said first capacitance means from an ON- state into an OFF- state, and thereafter reducing said second rate of change for the potential of said second electrode of said second capacitance means by reducing the absolute value of the difference between the potential of said second electrode of said second capacitance means and the potential of said first electrode of said second capacitance means below the absolute value of said threshold voltage of said second capacitance means thereby bringing said second capacitance means from an ON- state into an OFF- state with a delay of a prescribed period.

5. The semiconductor device according to claim 1 , reducing said second rate of change for the potential of said second electrode of either said first capacitance means or said second capacitance means by changing the potential of said first electrode of said first capacitance means and the potential of said first electrode of said second capacitance means from said first potential to said second potential at said first rate of change while reducing the absolute value of the difference between the potentials of said first and second electrodes of either said first capacitance means or said second capacitance means below the absolute value of said threshold voltage of corresponding said first or second capacitance means thereby bringing either said first capacitance means or said second capacitance means into an OFF- state.

6. The semiconductor device according to claim 1 , further comprising a boot circuit outputting a potential changing from said first potential to said second potential at a first rate of change to said first electrode of said first capacitance means and said first electrode of said second capacitance means.

7. The semiconductor device according to claim 6 , wherein

said boot circuit includes a first transistor having a threshold voltage substantially identical to that of either said first capacitance means or said second capacitance means, voltage change means reducing or increasing the potential of the source region or the drain region of said first transistor by a prescribed voltage and a second transistor for changing the potential of the source region or the drain region of said first transistor to said second potential at said first rate of change,

for inputting a potential substantially identical to said potential input in said second electrode of either said first capacitance means or said second capacitance means in the gate electrode of said first transistor when the potential of said first electrode of either said first capacitance means or said second capacitance means is at said first potential.

8. The semiconductor device according to claim 7 , wherein

said voltage change means includes either a high resistance or a transistor.

9. The semiconductor device according to claim 1 , comprising a plurality of potential difference enlarging circuits including said first capacitance means and said second capacitance means,

for enlarging the difference between said potential input in said second electrode of said first capacitance means and said potential input in said second electrode of said second capacitance means a plurality of times through said plurality of potential difference enlarging circuits.

10. The semiconductor device according to claim 9 , wherein

said plurality of potential difference enlarging circuits include:

a first potential difference enlarging circuit including first conductivity type said first capacitance means and first conductivity type said second capacitance means, and

a second potential difference enlarging circuit including second conductivity type said first capacitance means and second conductivity type said second capacitance means, wherein

said semiconductor device inputs said first potential in said second electrode of said first conductivity type first capacitance means and said second electrode of said second conductivity type first capacitance means while inputting said second potential in said second electrode of said first conductivity type second capacitance means and said second electrode of said second conductivity type second capacitance means, and

enlarges the difference between said first potential input in said second electrode of said first conductivity type first capacitance means and said second potential input in said second electrode of said first conductivity type second capacitance means through said first potential difference enlarging circuit and thereafter enlarging the difference between said first potential in said second electrode of said second conductivity type first capacitance means and said second potential in said second electrode of said second conductivity type second capacitance means.

11. The semiconductor device according to claim 1 , wherein

said first capacitance means includes a third transistor serving as a capacitor having different ON- and OFF- state capacitances,

said first electrode of said first capacitance means includes at least either the source region or the drain region of said third transistor,

said second electrode of said first capacitance means includes the gate electrode of said third transistor,

said second capacitance means includes a fourth transistor serving as a capacitor having different ON- and OFF- state capacitances,

said first electrode of said first capacitance means includes the gate electrode of said third translator,

said second electrode of said third transistor,

said second electrode of said first capacitance means includes at least either the source region or the drain region of said transistor,

said second capacitance means includes a fourth transistor serving as a capacitor having different ON- and OFF- state capacitances,

said first electrode of said second capacitance means includes the gate electrode of said fourth transistor, and

said second electrode of said second capacitance means includes at least either the source region or the drain region of said fourth transistor.

12. The semiconductor device according to claim 1 , wherein

said first capacitance means includes a third transistor serving as a capacitor having different ON- and OFF- state capacitances,

said first electrode of said first capacitance means includes the gate electrode of said third transistor,

said second electrode of said first capacitance means includes at least either the source region or the drain region of said third transistor,

said second capacitance means includes a fourth transistor serving as a capacitor having different ON- and OFF- state capacitances,

said first electrode of said second capacitance means includes the gate electrode of said fourth transistor, and

said second electrode of said second capacitance means includes at least either the source region or the drain region of said fourth transistor.

13. The semiconductor device according to claim 1 , wherein

said first capacitance means includes a third transistor serving as a capacitor having different ON- and OFF- state capacitances,

said second capacitance means includes a fourth transistor serving as a capacitor having different ON- and OFF- state capacitances, and

said ON- state capacitances of said third transistor and said fourth transistor are larger than said OFF- state capacitances.

14. The semiconductor device according to claim 13 , wherein

said third transistor and said fourth transistor have gate widths smaller than gate lengths.

15. The semiconductor device according to claim 1 , further comprising:

storage means holding data, and

a data line linked with said storage means and connected to said second electrode of either said first capacitance means or said second capacitance means,

for inputting a potential responsive to said data held in said storage means in said second electrode of either said first capacitance means or said second capacitance means through said data line while inputting a reference potential in said second electrode of either said second capacitance means or said first capacitance means when reading said data.

16. The semiconductor device according to claim 15 , wherein

said storage means includes either a ferroelectric capacitor or a capacitor.

17. The semiconductor device according to claim 15 , further comprising a driving line linked with said storage means,

for applying a voltage pulse to said storage means through said driving line when reading said data thereby inputting a negative potential in said second electrode of either said first capacitance means or said second capacitance means from said storage means through said data line if said storage means holds first data while inputting a positive potential in said second electrode of either said first capacitance means or said second capacitance means from said storage means through said data line if said storage means holds second data.

18. The semiconductor device according to claim 17 , wherein

said storage means includes a ferroelectric capacitor having a ferroelectric film provided between a word line and a bit line arranged to intersect with each other.

19. A semiconductor device comprising:

first capacitance means and second capacitance means having different ON- and OFF- state capacitances, for changing the potential of a first electrode of said first capacitance means and the potential of a first electrode of said second capacitance means from a first potential to a second potential thereby enlarging the difference between a potential input in a second electrode of said first capacitance means and a potential input in a second electrode of said second capacitance means and comparing said potential input in said second electrode of said first capacitance means and said potential input in said second electrode of said second capacitance means with each other; and

a determination circuit determining whether the potential of said second electrode of either said first capacitance means or said second capacitance means is higher or lower than the potential of said second electrode of either said second capacitance means or said first capacitance means by comparing the potential of said second electrode of said first capacitance means and the potential of said second electrode of said second capacitance means after said enlargement of said potential difference with each other.

20. The semiconductor device according to claim 19 , wherein

said determination circuit includes a sense amplifier determining whether the potential of said second electrode of either said first capacitance means or said second capacitance means is higher or lower than the potential of said second electrode of either said second capacitance means or said first capacitance means by further amplifying the difference between the potential of said second electrode of said first capacitance means and the potential of said second electrode of said first capacitance means and the potential of said second electrode of said second capacitance means after said enlargement of said potential difference and thereafter comparing the potential of said second electrode of said first capacitance means and the potential of said second electrode of said second capacitance means with each other.