IP Library Granted Patent US 7,518,230
Granted Patent B2
US 7,518,230 · App. 11/637,945 · Granted Apr 14, 2009

Semiconductor chip and semiconductor device

Assignee: Rohm Co., Ltd
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,518,230
App. No.
11/637,945
Granted
Apr 14, 2009
Kind
B2
Abstract

A semiconductor chip according to the present invention is a semiconductor chip having a circuit forming region, in which an internal circuit including a function element is formed, on the middle portion of the surface thereof, and having the surface thereof opposed to and joined to the surface of a solid-state device. The semiconductor chips includes: a plurality of bumps, formed so as to be ridged on the surface and brought into contact with the surface of the solid-state device, for electrically connecting the internal circuit with the solid-state device; power source wiring, formed in the surrounding region of the circuit forming region, to which power source voltage is supplied; ground wiring, formed in the surrounding region of the circuit forming region, which is grounded to ground potential; and protection elements, formed between the power source wiring and the ground wiring, which electrically intervenes between the bumps and the power source wiring and between the bumps and the ground wiring, respectively.

Claims (7)

1. A semiconductor chip having a circuit forming region, in which an internal circuit including a function element is formed, on the middle portion of a surface thereof, and having the surface thereof opposed to and joined to a surface of a solid-state device, comprising:

a plurality of bumps, formed so as to be ridged on the surface and brought into contact with the surface of the solid-state device, for electrically connecting the internal circuit with the solid-state device;

power source wiring, formed in a surrounding region of the circuit forming region, to which power source voltage is supplied;

ground wiring, formed in the surrounding region of the circuit forming region, which is grounded to ground potential; and

protection elements, formed between the power source wiring and the ground wiring, which electrically intervene between the bumps and the power source wiring and between the bumps and the ground wiring, respectively.

2. The semiconductor chip according to claim 1 , wherein the solid-state device is a semiconductor chip separate from the semiconductor chip.

3. The semiconductor chip according to claim 1 , wherein the solid-state device is a wiring substrate.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2020
From: ACHLYS TECHNOLOGIES INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 052957/0699 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2020
From: ROHM CO., LTD.
To: ACHLYS TECHNOLOGIES INC.
Reel/Frame 052273/0877 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2007
From: MIYATA, OSAMU; MORIFUJI, TADAHIRO
To: ROHM CO., LTD.
Reel/Frame 019015/0889 →
Priority Claims (2)
JP 2005-360590 · Dec 14, 2005 · national
JP 2005-363836 · Dec 16, 2005 · national
Continuity (1)
Related Publication 20070145565A1 · Jun 28, 2007