Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same
View Patent ↗Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor device with a backside integrated inductor includes a semiconductor substrate having a frontside, a backside and a buried insulating layer interposed between the front and backsides of the substrate. An integrated circuit is formed on the frontside of the semiconductor substrate and an integrated inductor is formed on the backside of the semiconductor substrate. An interconnection structure is formed through the buried insulating layer to connect the integrated inductor to the integrated circuit. The semiconductor substrate may be an SOI (silicon on insulator) structure.
1. A method of forming a semiconductor device, comprising:
forming an integrated circuit on a frontside of a semiconductor substrate;
forming an integrated inductor within a backside insulating layer on a backside of the semiconductor substrate;
forming an interconnection structure through a buried insulating layer interposed between the frontside and backside of the semiconductor substrate, which connects the integrated inductor to the integrated circuit;
forming a ground plane within the backside insulating layer on the backside of the semiconductor substrate,
wherein forming the integrated inductor structure comprises:
filling a first plurality of via holes etched in a the backside insulating layer to form backside contact plugs;
filling a trench etched in the backside insulating layer to form an inductor coil, wherein the backside contact plugs form part of the interconnection structure for connecting the inductor coil to the frontside integrated circuit;
filling a second plurality of via holes in the backside insulating layer to form backside dummy contact plugs to support the integrated inductor, wherein the backside dummy contact plugs each have one end embedded in the backside of the semiconductor substrate and do not form part of the interconnection structure for connecting the inductor coil to the frontside integrated circuit; and
forming an air gap surrounding the integrated inductor by removing insulation material from the backside insulating layer.
2. The method of claim 1 , wherein the semiconductor substrate is SOI (silicon on insulator) structure.
3. The method of claim 1 , wherein forming the interconnection structure comprises:
forming a through-wafer frontside contact plug having a first end in the buried insulating layer of the semiconductor substrate and a second end contacting a frontside metal level; and
forming a through-wafer backside contact plug having a first end in the buried insulating layer of the semiconductor substrate and a second end contacting an inductor coil structure such that the first ends of the through-wafer frontside and backside contact plugs are electrically contacted to each other.
4. The method of claim 1 , wherein forming the integrated inductor on the backside of the semiconductor comprises forming one or more layers of metal embedded in the backside insulating layer.
5. The method of claim 1 , wherein forming the ground plane comprises forming insulating islands formed by oxygen ion implantation on in the backside insulation layer of the semiconductor substrate.
6. The method of claim 1 , wherein forming the ground plane comprises forming a shallow trench isolation pattern formed on in the backside insulation layer of the semiconductor substrate.
7. The method of claim 1 , wherein forming the ground plane comprises forming doped regions of silicon on in the backside insulation layer of the semiconductor substrate.
8. A method of forming a semiconductor device, comprising:
forming an integrated circuit on a frontside of a semiconductor substrate;
forming an integrated inductor within a backside insulating layer on a backside of the semiconductor substrate;
forming an interconnection structure through a buried insulating layer interposed between the frontside and backside of the semiconductor substrate, which connects the integrated inductor to the integrated circuit; and
forming a ground plane disposed between the backside integrated inductor and the frontside integrated circuit, wherein forming the ground plane comprises forming insulating islands formed by oxygen ion implantation on the backside of the semiconductor substrate.
9. The method of claim 8 , wherein the semiconductor substrate is SOI (silicon on insulator) structure.
10. The method of claim 8 , wherein forming the interconnection structure comprises:
forming a through-wafer frontside contact plug having a first end in the buried insulating layer of the semiconductor substrate and a second end contacting a frontside metal level; and
forming a through-wafer backside contact plug having a first end in the buried insulating layer of the semiconductor substrate and a second end contacting an inductor coil structure such that the first ends of the through-wafer frontside and backside contact plugs are electrically contacted to each other.
11. The method of claim 8 , wherein forming the integrated inductor on the backside of the semiconductor comprises forming one or more layers of metal embedded in the backside insulating layer.