Semiconductor device and method of controlling the same

1. A semiconductor device comprising:

a plurality of memory regions that include non-volatile memory cells;

a plurality of disabling information memory units that correspond to the memory regions, each of the disabling information memory units storing first program disabling information indicating whether programming is to be disabled or enabled in each corresponding memory region;

a program disabling information selection circuit that outputs second program disabling information for disabling programming in a corresponding memory region, regardless of the first program disabling information, when programming is disabled collectively in the memory regions in accordance with collective program disabling information indicating whether programming is to be disabled collectively in the memory regions, the program disabling information selection circuit outputting the first program disabling information as the second program disabling information when programming is not collectively disabled; and

a program control circuit that disables or enables programming in the corresponding memory region in accordance with the second program disabling information.

2. The semiconductor device as claimed in claim 1 , further comprising

a collective disabling information memory unit that stores the collective program disabling information.

3. The semiconductor device as claimed in claim 1 , further comprising

a disabling information control circuit that prohibits a change of the first program disabling information from a program disabling state to a program enabling state, after the first program disabling information is switched to the program disabling state.

4. The semiconductor device as claimed in claim 3 , further comprising

a ROM information memory unit that stores ROM information indicating whether a change of the first program disabling information from the program disabling state to the program enabling state is prohibited, after the first program disabling information is switched to the program disabling state,

wherein the disabling information control circuit prohibits the change of the first program disabling information from the program disabling state to the program enabling state in accordance with the ROM information after the first program disabling information is switched to the program disabling state.

5. The semiconductor device as claimed in claim 2 , wherein the disabling information memory units and the collective disabling information memory unit use different commands from each other.

6. The semiconductor device as claimed in claim 2 , wherein an erasing unit for erasing the first program disabling information in the disabling information memory units is different from an erasing unit for erasing the collective program disabling information in the collective disabling information memory unit.

7. A method of controlling a semiconductor device that has a plurality of memory regions including a plurality of non-volatile memory cells, the method comprising the steps of:

setting second program disabling information in a program disabling state, regardless of first program disabling information indicating whether programming is to be disabled or enabled in a corresponding memory region, when programming is disabled collectively in the memory regions in accordance with collective program disabling information indicating whether programming is to be disabled or enabled collectively in the memory regions, and setting the first program disabling information as the second program disabling information when programming is not collectively disabled; and

disabling or enabling programming in the corresponding memory region in accordance with the second program disabling information.

8. The method as claimed in claim 7 , further comprising the step of

prohibiting a change of the first program disabling information from a program disabling state to a program enabling state, after the first program disabling information is switched to the program disabling state.

9. A semiconductor device comprising:

a plurality of memory regions that include non-volatile memory cells;

a plurality of disabling information memory units that correspond to the memory regions, each of the disabling information memory units storing program disabling information indicating whether programming is to be disabled or enabled in each corresponding memory region;

an input terminal that inputs auxiliary program disabling information indicating whether a change of the program disabling information from a program enabling state and to a program disabling state for a corresponding memory unit is allowed; and

a disabling information control circuit that allows or does not allow a change of the program disabling information from the program enabling state to the program disabling state for the corresponding memory region in accordance with the auxiliary program disabling information when auxiliary information nullifying information indicating whether the auxiliary program disabling information is to be nullified or validated indicates that the auxiliary program disabling information is valid, the disabling information control circuit allowing a change of the program disabling information from the program enabling state to the program disabling state for the corresponding memory region, regardless of the auxiliary program disabling information, when the auxiliary information nullifying information indicates that the auxiliary program disabling information is invalid.

10. The semiconductor device as claimed in claim 9 , further comprising

an auxiliary information nullifying information memory unit that stores the auxiliary information nullifying information.

11. The semiconductor device as claimed in claim 9 , wherein the disabling information control circuit prohibits a change of the program disabling information from the program disabling state to the program enabling state for the corresponding memory region, after the program disabling information is switched to the program disabling state for the corresponding memory state in accordance with ROM information indicating whether to prohibit a change of the program disabling information from the program disabling state to the program enabling state for the corresponding memory region.

12. The semiconductor device as claimed in claim 9 , wherein, when ROM information indicating whether to prohibit a change of the program disabling information from the program disabling state to the program enabling state for the corresponding memory region indicates that the change from the program disabling state to the program enabling state is not prohibited, a change of the program disabling information from the program enabling state to the program disabling state is allowed or not allowed in accordance with the auxiliary program disabling information, regardless of the auxiliary information nullifying information.

13. The semiconductor device as claimed in claim 10 , wherein the disabling information memory units and the auxiliary information nullifying information memory unit use different commands from each other.

14. The semiconductor device as claimed in claim 9 , wherein an erasing unit for erasing the program disabling information in the disabling information memory units is different from an erasing unit for erasing the auxiliary information nullifying information in the auxiliary information nullifying information memory unit.

15. A method of controlling a semiconductor device that has a plurality of memory regions including a plurality of non-volatile memory cells, the method comprising the steps of:

inputting auxiliary program disabling information indicating whether to allow a change of program disabling information from a program enabling state to a program disabling state, the program disabling information indicating whether programming is to be disabled or enabled in each corresponding memory region; and

allowing or not allowing a change of the program disabling information from the program enabling state to the program disabling state for the corresponding memory region when the auxiliary program disabling information is valid in accordance with auxiliary information nullifying information indicating whether the auxiliary program disabling information is to be nullified or validated, and allowing a change of the program disabling information from the program enabling state to the program disabling state for the corresponding memory region, regardless of the auxiliary program disabling information, when the auxiliary information nullifying information indicates that the auxiliary program disabling information is invalid.

16. The method as claimed in claim 15 , further comprising the step of

prohibiting a change of the program disabling information from the program disabling state to the program enabling state, after the program disabling information is switched to the program disabling state in accordance with ROM information indicating whether to prohibit a change of the program disabling information from the program disabling state to the program enabling state for the corresponding memory region.

17. A semiconductor device comprising:

a plurality of memory regions that include non-volatile memory cells;

a plurality of disabling information memory units that correspond to the memory regions, each of the disabling information memory units storing program disabling information indicating whether programming is to be disabled or enabled in each corresponding memory region;

a disabling information control circuit that prohibits a change of the program disabling information from a program disabling state to a program enabling state, after the program disabling information is switched to the program disabling state; and

a group erasing control circuit that performs erasing collectively in the memory regions in accordance with group erasing information,

the group erasing control circuit nullifying or validating the group erasing information in accordance with group erasing nullifying information indicating whether the group erasing information is to be nullified or validated.

18. The semiconductor device as claimed in claim 17 , further comprising

a group erasing nullifying information memory unit that stores the group erasing nullifying information.

19. The semiconductor device as claimed in claim 17 , wherein the disabling information control circuit outputs the group erasing nullifying information for nullifying the group erasing information to the group erasing control circuit, when at least one piece of the program disabling information is switched to a program disabling state.

20. The semiconductor device as claimed in claim 17 , wherein:

the memory regions are divided into a plurality of groups;

collective erasing can be performed in each of the groups of memory regions; and

the number of pieces of the group erasing information is the same as the number of the groups.

21. The semiconductor device as claimed in claim 19 , wherein the disabling information control circuit outputs the group erasing nullifying information for nullifying the group erasing information as to one of the groups to the group erasing control circuit, when programming is disabled in the disabling information memory unit corresponding to at least one of the memory regions in the one of the groups.

22. The semiconductor device as claimed in claim 18 , wherein the disabling information memory units and the group erasing nullifying information memory unit use different commands from each other.

23. The semiconductor device as claimed in claim 18 , wherein an erasing unit for erasing the program disabling information in the disabling information memory units is different from an erasing unit for erasing the group erasing nullifying information in the group erasing nullifying information memory unit.

24. A method of controlling a semiconductor device that has a plurality of memory regions including non-volatile memory cells, the method comprising the steps of:

prohibiting a change of program disabling information from a program disabling state to a program enabling state, after the program disabling information is switched to the program disabling state, the program disabling information indicating whether programming is to be disabled or enabled in each corresponding memory region;

performing erasing collectively in the memory regions in accordance with group erasing information indicating collective erasing in the memory regions; and

nullifying or validating the group erasing information.

25. The method as claimed in claim 24 , wherein the group erasing information is nullified when at least one piece of the program disabling information is switched to the program disabling state.