Copper metal interconnection with a local barrier metal layer
View Patent ↗Embodiments relate to a method of forming a copper metal interconnection in a semiconductor device using a damascene process. In embodiments, the method may include forming a damascene pattern in an interlayer dielectric layer on a semiconductor substrate, burying a copper plating layer in the damascene pattern using an ECP method, forming a recess on the copper plating layer buried in the damascene pattern, and forming a barrier metal layer in the recess. Since the barrier metal layer may be locally formed on the copper metal interconnection, it may be possible to prevent the diffusion of the copper although the size of the pattern is small.
1. A method, comprising:
forming a damascene pattern in an interlayer dielectric layer over a semiconductor substrate;
forming a copper plating layer in the damascene pattern by performing an electrochemical plating (ECP), wherein the copper plating layer being thickly formed on a surface of the interlayer dielectric layer;
forming a recess in the damascene pattern by performing a deplating process of apply back current to the substrate; and
forming a barrier metal layer in the recess over the copper plating layer.
2. The method of claim 1 , wherein forming the barrier metal layer comprises:
forming the barrier metal layer over the interlayer dielectric layer, including over the recess; and
planarizing a surface of the substrate to remove a part of the barrier metal layer formed over the interlayer dielectric layer to expose the interlayer dielectric layer.
3. The method of claim 2 , wherein the barrier metal layer comprises at least one of Ta, TaN, a double layer of TaN/Ta, TaSiN, Ru, TiSiN, and WNx.
4. The method of claim 1 , wherein the barrier metal layer is formed locally over the copper plating layer formed in the damascene pattern.
5. The method of claim 1 , wherein the barrier metal layer comprises at least one of Ta, TaN, a double layer of TaN/Ta, TaSiN, Ru, TiSiN, and WNx.