Insulated gate semiconductor device
Channel regions and gate electrodes are also disposed continuously with transistor cells below a gate pad electrode. The transistor cells are formed in a stripe pattern and allowed to contact a source electrode. In this way, the channel regions and the gate electrodes, which are positioned below the gate pad electrode, are kept at a predetermined potential. Thus, a predetermined drain-source reverse breakdown voltage can be secured without providing a p+ type impurity region on the entire surface below the gate pad electrode.
1. An insulated gate semiconductor device comprising:
a semiconductor substrate of a first general conductivity type;
a plurality of gate electrodes formed on the semiconductor substrate and arranged in a first stripe pattern;
a plurality of channel regions of a second general conductivity type formed on the semiconductor substrate and arranged in a second stripe pattern, the first and second stripe patterns being oriented in a first direction;
a first insulating film disposed between the channel regions and the gate electrodes;
a plurality of source regions of the first general conductivity type formed in corresponding channel regions and arranged in a third stripe pattern oriented in the first direction;
a second insulating film disposed on the gate electrodes; and
a gate pad electrode disposed on the second insulating film so as to overlay part of the channel regions,
wherein there is no source region formed in the part of the channel regions overlaid by the gate pad electrode.
2. The insulated gate semiconductor device of claim 1 , further comprising a plurality of contact holes formed in the second insulating film and a source electrode disposed on the second insulating film so as to contact, through the contact holes, corresponding source regions formed in the channel regions.
3. The insulated gate semiconductor device of claim 1 , further comprising a gate extraction electrode disposed in a periphery of the semiconductor substrate and connecting the gate electrodes and the gate pad electrode, and a high-concentration region of the second general conductivity type formed on the substrate below the gate extraction electrode and connected with the channel regions.
4. The insulated gate semiconductor device of claim 2 , wherein the channel regions located below the gate pad electrode are electrically connected with the source electrode.
5. The insulated gate semiconductor device of claim 1 , wherein the gate electrodes are disposed in corresponding trenches formed in the semiconductor substrate so as to follow the second stripe pattern.
6. The insulated gate semiconductor device of claim 3 , wherein part of the gate extraction electrode and part of the gate electrode are located below the gate pad electrode.
7. An insulated gate semiconductor device comprising:
a semiconductor substrate of a first general conductivity type;
a plurality of gate electrodes formed on the semiconductor substrate and arranged in a first stripe pattern;
a plurality of channel regions of a second general conductivity type formed on the semiconductor substrate and arranged in a second stripe pattern, the first and second stripe patterns being oriented in a first direction;
a first insulating film disposed between the channel regions and the gate electrodes;
a plurality of source regions of the first general conductivity type formed in corresponding channel regions and arranged in a third stripe pattern oriented in the first direction;
a second insulating film disposed on the gate electrodes;
a gate pad electrode disposed on the second insulating film;
a gate extraction electrode disposed in a periphery of the semiconductor substrate and connecting the gate electrodes and the gate pad electrode; and
a high-concentration region of the second general conductivity type formed on the substrate below the gate extraction electrode and connected with the channel regions,
wherein part of the channel regions, part of the gate extraction electrode and part of the gate electrodes are located below the gate pad electrode and corresponding portion of the second insulating film, and no part of the source regions is located below the gate pad electrode.