Electronic device including a trench and a conductive structure therein
An electronic device can include a transistor. In an embodiment, the transistor can include a semiconductor layer having a primary surface and a conductive structure. The conductive structure can include a horizontally-oriented doped region lying adjacent to the primary surface, an underlying doped region spaced apart from the primary surface and the horizontally-oriented doped region, and a vertically-oriented conductive region extending through a majority of the thickness of the semiconductor layer and electrically connecting the doped horizontal region and the underlying doped region. In another embodiment, the transistor can include a gate dielectric layer, wherein the field-effect transistor is designed to have a maximum gate voltage of approximately 20 V, a maximum drain voltage of approximately 30 V, and a figure of merit no greater than approximately 30 mΩ*nC.
1. An electronic device comprising a transistor, wherein the transistor comprises:
a semiconductor layer having a primary surface and a trench extending from the primary surface;
a conductive structure comprising:
a horizontally-oriented doped region lying adjacent to the primary surface;
an underlying doped region spaced apart from the primary surface and the horizontally-oriented doped region; and
a vertically-oriented conductive region extending through a majority of the thickness of the semiconductor layer, including a conductive layer that substantially fills the trench, and electrically connecting the horizontally-oriented doped region and the underlying doped region;
a conductive electrode overlying and electrically insulated from the conductive structure, wherein the conductive electrode is configured to be at a substantially constant voltage when the electronic device is in a normal operating state;
a gate electrode overlying the primary surface of the semiconductor layer; and
a gate signal line overlying the primary surface of the semiconductor layer and the conductive structure, wherein within an area occupied by the transistor, the gate signal line overlies the conductive electrode.
2. The electronic device of claim 1 , wherein the vertically-oriented conductive region comprises an elevated portion that overlies the primary surface of the semiconductor layer.
3. The electronic device of claim 2 , wherein the elevated portion has an uppermost surface that lies at an elevation higher than a lowermost surface of the gate electrode.
4. The electronic device of claim 1 , wherein:
the semiconductor layer comprises a compensating region;
the compensating region lies between the horizontally-oriented doped region and the underlying doped region and extends substantially to the vertically-oriented conductive region; and
the compensating region has conductivity type opposite that of the horizontally-oriented doped region and the underlying doped region.
5. The electronic device of claim 1 , wherein the vertically-oriented conductive structure comprises a conductive plug.
6. The electronic device of claim 5 , wherein the conductive plug comprises doped polycrystalline silicon.
7. The electronic device of claim 5 , wherein the conductive plug comprises a refractory metal.
8. The electronic device of the claim 1 , further comprising:
a source region lying adjacent to the primary surface; and
a well region lying adjacent to the primary surface, wherein a portion of the well region is a channel region for the transistor and lies between the source region and the horizontally-oriented doped region.
9. The electronic device of claim 8 , further comprising:
a well contact region lying adjacent to the source region; and
an interconnect contacting the source region and the well contact region.
10. The electronic device of claim 9 , wherein the electronic device is configured such that when the electronic device would be in a normal operating state, a principal charge carrier flow is from the source region to the underlying doped region via the well region, horizontally-oriented doped region, and the vertically-oriented conductive structure.
11. The electronic device of claim 8 , further comprising a gate electrode overlying portions of the source region and the channel region.
12. The electronic device of claim 1 , wherein an interconnect does not overlie and contact the horizontally-oriented doped region or the vertically-oriented conductive region.
13. An electronic device comprising:
a semiconductor layer having a primary surface and a trench extending from the primary surface;
a conductive structure comprising:
a horizontally-oriented doped region lying adjacent to the primary surface, wherein a portion of a well region lies between a source region and the horizontally-oriented doped region;
an underlying doped region spaced apart from the primary surface; and
a vertically-oriented conductive region lying between the horizontally-oriented doped region and the underlying doped region, wherein the vertically-oriented conductive region including a conductive layer that substantially fills the trench;
a source region lying adjacent to the primary surface;
a well region lying adjacent to the primary surface, wherein a portion of the well region includes a channel region that lies between the source region and the horizontally-oriented doped region;
a gate electrode overlying the channel region; and
a conductive electrode configured to be at a substantially constant voltage when the electronic device is in a normal operating state, wherein:
the conductive electrode overlies and is electrically insulated from the conductive structure;
a portion of the conductive electrode lies adjacent to the gate electrode;
the conductive electrode has a first surface and a second surface opposite the first surface;
the primary surface is closer to the first surface than the second surface; and
within an area occupied by the transistor, each of the first and second surfaces of the conductive electrode lies at elevations between lowermost and uppermost points of the gate electrode.
14. The electronic device of claim 13 , further comprising a gate signal line overlying the primary surface of the semiconductor layer and the conductive structure, wherein within the transistor, the gate signal line overlies the conductive electrode.
15. The electronic device of claim 13 , wherein the horizontally-oriented doped region extends approximately 0.2 to 2.0 microns along the primary surface from the vertically-oriented conductive region toward the source region.
16. The electronic device of claim 14 , wherein:
the semiconductor layer has a thickness no greater than approximately 5 microns;
a portion of the semiconductor layer lies outside of the well region, the source region, the horizontally-oriented doped region, and the vertically-oriented conductive region; and
the portion of the semiconductor layer has a dopant concentration of no greater than approximately 1×10 16 atoms/cm 3 .
17. The electronic device of claim 16 , wherein the dopant concentration is no greater than approximately 1×10 15 atoms/cm 3 .
18. The electronic device of claim 16 , wherein the portion of the semiconductor layer, the source region, the horizontally-oriented doped region, and the underlying doped region have a same conductivity type.
19. The electronic device of claim 16 , wherein:
the portion of the semiconductor layer and the well region have a first conductivity type; and the source region, the horizontally-oriented doped region, and the underlying doped region has a second conductivity type opposite the first conductivity type.
20. The electronic device of claim 16 , wherein:
the horizontally-oriented doped region has a peak dopant concentration of at least approximately 2×10 17 atoms/cm 3 ; and
each of the vertically-oriented conductive region and the underlying doped region has a peak dopant concentration of at least approximately 1×10 19 atoms/cm 3 .
21. The electronic device of claim 20 , wherein the peak dopant concentration of the horizontally-oriented doped region is no greater than approximately 2×10 18 atoms/cm 3 .
22. The electronic device of claim 13 , wherein an interconnect does not overlie and contact the horizontally-oriented doped region or the vertically-oriented conductive region.