Methods of forming electrical interconnects using electroless plating techniques that inhibit void formation
View Patent ↗Methods of forming electrical interconnects include forming a copper pattern on a semiconductor substrate and then forming an electrically insulating capping layer on the copper pattern and an interlayer insulating layer on the electrically insulating capping layer. A contact hole is then formed, which extends through the interlayer insulating layer and the electrically insulating capping layer and exposes an upper surface of the copper pattern. An electroless plating step is then performed to form a copper pattern extension onto the exposed upper surface of the copper pattern. The copper pattern extension may have a thickness that is less than a thickness of the electrically insulating capping layer, which may be formed as a SiCN layer.
1. A method of forming an electrical interconnect, comprising:
forming a copper pattern on a semiconductor substrate;
forming an electrically insulating capping layer on the copper pattern;
forming an interlayer insulating layer on the electrically insulating capping layer;
forming a contact hole that extends through the interlayer insulating layer and the electrically insulating capping layer and exposes an upper surface of the copper pattern; and
electroless plating a copper pattern extension onto the exposed upper surface of the copper pattern;
wherein a portion of the interlayer insulating layer extending adjacent the electrically insulating capping layer has a nonuniform composition; wherein forming a contact hole comprises forming a contact hole having a non-uniform width therein with a constricted neck at an interface between the electrically insulating capping layer and the interlayer insulating layer; and wherein a minimum width of the non-uniformly wide contact hole in the electrically insulating capping layer is at the interface.
2. The method of claim 1 , wherein a thickness of the copper pattern extension is less than a thickness of the electrically insulating capping layer.
3. The method of claim 2 , wherein the electrically insulating capping layer comprises SiCN.
4. The method of claim 1 , wherein the electrically insulating capping layer comprises SiCN.
5. The method of claim 1 , wherein said electroless plating is preceded by:
depositing a first barrier metal layer onto a sidewall of the contact hole and onto the exposed upper surface of the copper pattern; and
selectively etching back a portion of the first barrier metal layer to thereby expose the upper surface of the copper pattern.
6. The method of claim 5 , wherein selectively etching back a portion of the first barrier metal layer is followed by:
depositing a second barrier metal layer onto the exposed upper surface of the copper pattern extension; and
electroplating a copper interconnect into the contact hole.
7. The method of claim 1 , wherein said electroless plating is followed by:
depositing a barrier metal layer onto a sidewall of the contact hole and onto the copper pattern extension; and
electroplating a copper interconnect into the contact hole.
8. The method of claim 1 , wherein the portion of the interlayer insulating layer extending adjacent the electrically insulating capping layer is a graded oxide layer.
9. A method of forming an electrical interconnect, comprising:
forming a copper pattern on a semiconductor substrate;
forming an electrically insulating capping layer comprising a first material, on the copper pattern;
forming an interlayer insulating layer comprising a second material different from the first material, on the electrically insulating capping layer;
forming a contact hole that extends through the interlayer insulating layer and the electrically insulating capping layer and exposes an upper surface of the copper pattern; and
electroless plating a metal extension onto the exposed upper surface of the copper pattern;
wherein a portion of the interlayer insulating layer extending adjacent the electrically insulating capping layer has a nonuniform composition; wherein forming a contact hole comprises forming a contact hole having a non-uniform width therein with a constricted neck at an interface between the electrically insulating capping layer and the interlayer insulating layer; and wherein a minimum width of the non-uniformly wide contact hole in the electrically insulating capping layer is at the interface.
10. The method of claim 9 , wherein the metal extension comprises a metal selected from a group consisting of copper and cobalt.
11. The method of claim 10 , wherein a thickness of the metal extension is less than a thickness of the electrically insulating capping layer.
12. The method of claim 11 , wherein the electrically insulating capping layer comprises SiCN.
13. The method of claim 10 , wherein the metal extension comprises a material selected from a group consisting of copper, CoW, CoWP, CoWPB and CoWB.
14. The method of claim 9 , wherein the electrically insulating capping layer comprises SiCN.
15. The method of claim 9 , wherein said electroless plating is preceded by:
depositing a first barrier metal layer onto a sidewall of the contact hole and onto the exposed upper surface of the copper pattern; and
selectively etching back a portion of the first barrier metal layer to thereby expose the upper surface of the copper pattern.
16. The method of claim 15 , wherein selectively etching back a portion of the first barrier metal layer is followed by:
depositing a second barrier metal layer onto the exposed upper surface of the metal extension; and
electroplating a copper interconnect into the contact hole.
17. The method of claim 9 , wherein said electroless plating is followed by:
depositing a barrier metal layer onto a sidewall of the contact hole and onto the metal extension; and
electroplating a copper interconnect into the contact hole.
18. The method of claim 9 , wherein the portion of the interlayer insulating layer extending adjacent the electrically insulating capping layer is a graded oxide layer.