Self-aligned metal-semiconductor alloy and metallization for sub-lithographic source and drain contacts
View Patent ↗A lateral double-gate FET structure with sub-lithographic source and drain regions is disclosed. The sub-lithographic source and drain regions are defined by a sacrificial spacer. Self-aligned metal-semiconductor alloy and metal contacts are made to the sub-lithographic source and drain using conventional silicon processing.
1. A double-gate field effect transistor (FET) comprising:
a single-crystal semiconductor channel located within a single-crystal semiconductor film;
a top-gate and a back-gate on either side of the single-crystal semiconductor channel for controlling the current through the single-crystal semiconductor channel;
a source region and a drain region adjacent to the single-crystal semiconductor channel and located within the single-crystal semiconductor film, said source and drain regions have a lateral size of 0.1 microns or less;
a metal-semiconductor alloy region located on and self-aligned to an exposed horizontal surface of both the source region and the drain region; and
a buried metal line connecting to an edge of each of said metal-semiconductor alloy regions.
2. The double-gate FET of claim 1 further comprising a metal stud connecting to each of the buried metal lines.
3. The double-gate FET of claim 1 wherein said single-crystal semiconductor channel comprises a Si-containing semiconductor, and said metal-semiconductor alloy comprises a silicide.
4. The double-gate FET of claim 1 wherein said top-gate and said bottom-gate are comprised of doped polySi or doped SiGe.
5. The double-gate FET of claim 1 further comprises a top-gate dielectric located between said top-gate and said single-crystal semiconductor channel and a bottom-gate dielectric located between said bottom-gate and said single-crystal semiconductor channel.
6. The double-gate FET of claim 1 wherein each of said buried metal lines is comprised of one of Ni, Ti, Pt, W and Co.
7. The double-gate FET of claim 1 wherein said metal-semiconductor alloy is one of NiSi, CoSi 2 , TiSi 2 , and PtSi 2 .
8. The double-gate FET of claim 1 further comprising a raised source and raised drain formed on top of said source region and said drain region.
9. The double-gate FET of claim 2 wherein each of said metal studs comprises Al, W, Cu or AlCu.
10. A double-gate field effect transistor (FET) comprising:
a single-crystal Si channel located with a single-crystal Si layer;
a top-gate and a back-gate on either side of the single-crystal Si channel for controlling the current through the single-crystal Si channel;
a source region and a drain region adjacent to the single-crystal Si channel and located within said single-crystal Si layer, said source and drain regions have a lateral size of 0.1 microns or less;
a raised source and raised drain fanned on top of said source region and said drain region;
a silicide region located on and self-aligned to exposed horizontal surface of both said raised source and said raised drain, and over the top-gate;
a buried metal line connecting to an edge of each of said silicide regions; and
a metal stud connecting to each of the buried metal lines.
11. The double-gate FET of claim 10 wherein said top-gate and said bottom-gate are comprised of doped polySi or doped SiGe.
12. The double-gate FET of claim 10 further comprises a top-gate dielectric located between said top-gate and said single-crystal Si channel and a bottom-gate dielectric located between said bottom-gate and single-crystal Si channel.
13. The double-gate FET of claim 10 wherein each of said buried metal lines is comprised of one of Ni, Ti, Pt, W and Co.
14. The double-gate FET of claim 10 wherein each of said silicide regions is one of NiSi, CoSi 2 , TiSi 2 , and PtSi 2 .
15. The double-gate FET of claim 10 wherein each of said metal studs comprises Al, W, Cu or AlCu.