Advanced memory device having reduced power and improved performance

1. A memory device comprising:

a memory array storing data;

a variable delay controller periodically receiving delay commands from a first source external to the memory device during operation of the memory device, and outputting delay instruction bits responsive to the received delay commands;

a passive variable delay circuit:

receiving a clock from a second source external to the memory device;

receiving the delay instruction bits from the variable delay controller;

generating a delayed clock having a time relation to the received clock as determined by the delay instruction bits; and

outputting the delayed clock; an output driver:

receiving the data from the memory array and the delayed clock;

outputting the data at a time responsive to the delayed clock; and

a clock enable (CKE) pin, wherein the memory device transitions from a power down state to a calibration state in response to a serial pattern received on the CKE pin.

2. The memory device of claim 1 wherein the first source external to the memory device is a memory controller and the second source external to the memory device is the memory controller.

3. The memory device of claim 1 wherein the first source external to the memory device is a hub device and the second source external to the memory device is the hub device.

4. The memory device of claim 1 wherein the variable delay controller is an up/down counter and the delay instruction bits specify an amount of time to add or subtract from a previous delayed clock to generate the delayed clock.

5. The memory device of claim 1 wherein the variable delay controller is a mode register and the delay instruction bits specify a specific delay to apply to the received clock to generate the delayed clock.

6. The memory device of claim 1 wherein the delay command is a mode register set (MRS) command.