Efficient pitch multiplication process
Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.
1. A method for forming an integrated circuit, comprising:
providing a plurality of mask elements extending over an array and a periphery region of a partially fabricated integrated circuit;
providing a plurality of spacers extending in loops around sidewalls of the mask elements in the periphery region;
depositing a selectively definable layer over the mask elements and the spacers;
patterning the selectively definable layer to expose some of the spacers and the mask elements;
selectively removing exposed mask elements relative to the spacers and the selectively definable layer; and
subsequently transferring a pattern defined by spacers and mask elements to an underlying substrate.
2. The method of claim 1 , wherein each of the mask elements comprise a plurality of layers of material.
3. The method of claim 1 , further comprising providing an other plurality of spacers extending in loops around sidewalls of the mask elements in the array region.
4. The method of claim 3 , wherein providing the plurality of spacers and the other plurality of spacers comprises:
depositing a layer of spacer material on the plurality of mask elements; and
subjecting the layer of spacer material to a directional etch to form the plurality of spacers.
5. The method of claim 1 , wherein transferring the pattern comprises etching the pattern into the substrate.
6. The method of claim 1 , wherein the selectively definable layer comprises photoresist.
7. The method of claim 1 , wherein transferring the pattern defines a first set of interconnects in the array region and a second set of interconnects in the periphery region.
8. The method of claim 1 , wherein transferring the pattern defines interconnects extending from the array region into the periphery region, wherein a pitch between portions of the interconnects in the array region is less than a pitch between portions of the interconnects in the periphery region.
9. The method of claim 1 , further comprising selectively etching ends of the loops.
10. The method of claim 1 , wherein the pattern is defined in part by spacers disposed on sidewalls of the mask elements.
11. The method of claim 1 , wherein the mask elements comprise amorphous carbon.
12. A method for forming an integrated circuit, comprising:
simultaneously defining mask elements in an array region and a periphery region of a partially fabricated integrated circuit;
forming spacers at sidewalls of the mask elements in the array and the periphery regions;
depositing a selectively definable layer over the spacers and mask elements;
patterning the selectively definable layer;
transferring the pattern in the selectively definable layer to a level of the spacers and mask elements to form a consolidated pattern; and
transferring the consolidated pattern to an underlying substrate.
13. The method of claim 12 , further comprising transferring the consolidated pattern to an underying hardmask layer before transferring the consolidated pattern to the underlying substrate.
14. The method of claim 12 , wherein forming spacers comprises:
blanket depositing a layer of spacer material over the mask elements; and
anisotropically etching the layer of spacer material to define the spacers.
15. The method of claim 12 , wherein simultaneously defining mask elements comprises:
patterning a photoresist layer;
transferring a pattern from the photoresist layer to an underlying temporary layer to form the mask elements.
16. The method of claim 15 , wherein simultaneously defining mask elements further comprises transferring the pattern from the photoresist layer to a hard mask layer before transferring the pattern in the photoresist layer to the temporary layer, the mask elements comprising the hard mask layer and the temporary layer.
17. The method of claim 12 , wherein depositing the selectively definable layer comprises depositing photoresist.
18. The method of claim 12 , wherein patterning the selectively definable layer exposes some of the spacers in the array and the periphery regions.
19. The method of claim 12 , wherein some of the mask elements extend between the array and the periphery regions.
20. The method of claim 12 , wherein the partially fabricated integrated circuit is a partially fabricated memory device.