Asymmetrically stressed CMOS FinFET

1. A complementary metal oxide semiconductor (CMOS) device comprising a fin field effect transistor (FinFET) comprising:

at least one fin structure having a first end, a second end, a center section positioned laterally between said first end and said second end, a first side and a second side opposite said first side, said fin structure comprising:

a source region at said first end;

a drain region at said second end; and

a channel region in said center section between said source region said drain region;

a gate structure adjacent to said channel region on said first side and on said second side of said fin structure,

said channel region having a first portion in mechanical compression adjacent to said gate structure at said first side of said fin structure and further having a second portion in mechanical tension adjacent to said gate structure at said second side of said fin structure.

2. The CMOS device of claim 1 , said FinFET comprising an nFET and said nFET comprising an N-channel inversion region at said second side of said fin structure.

3. The CMOS device of claim 1 , said FinFET comprising a pFET and said pFET comprising a P-channel inversion region at said first side of said fin structure.

4. The CMOS device of claim 1 , said channel region comprising silicon.

5. The CMOS device of claim 1 , further comprising a tensile film on said second side of said fin structure and a relaxed film on said first side of said fin structure opposite said tensile film.

6. The CMOS device of claim 1 , further comprising an oxide cap layer over said fin structure.

7. A complementary metal oxide semiconductor (CMOS) device comprising a fin field effect transistor (FinFET) comprising:

at least one fin structure having a first end, a second end, a center section positioned laterally between said first end and said second end, a first side and a second side opposite said first side, said fin structure comprising:

a source region at said first end;

a drain region at said second end; and

a channel region in said center section between said source region from said drain region;

a gate structure adjacent to said channel region on said first side and on said second side of said fin structure; and

a relaxed film on said first side of said fin structure and a tensile film on said second side of said fin structure opposite said relaxed film such that said channel region has a first portion in mechanical compression adjacent to said gate structure at said first side of said fin structure and further has a second portion in mechanical tension adjacent to said gate structure at said second side of said fin structure.

8. The CMOS device of claim 7 , said FinFET comprising an nFET and said nFET comprising an N-channel inversion region at said second side of said fin structure.

9. The CMOS device of claim 7 , said FinFET comprising a pFET and said pFET comprising a P-channel inversion region at said first side of said fin structure.

10. The CMOS device of claim 7 , said channel region comprising silicon.

11. The CMOS device of claim 7 , said tensile film being adjacent to said source region and said drain region on said second side of said fin structure and said relaxed film being adjacent to said source region and said drain region on said first side of said fin structure.

12. The CMOS device of claim 7 , further comprising an oxide cap layer over said fin structure.

13. A method of forming a complementary metal oxide semiconductor (CMOS) device comprising a fin field effect transistor (FinFET), said method comprising:

forming at least one fin structure;

forming a gate structure adjacent to a channel region of said fin structure such that said gate structure is positioned on a first side of said fin structure and on a second side of said fin structure opposite said first side; and

forming differently strained films on said first side and said second side of said fin structure such that said channel region has a first portion in mechanical compression adjacent to said gate structure at said first side of said fin structure and further has second portion in mechanical tension adjacent to said gate structure at said second side of said fin structure.

14. The method of claim 13 , said FinFET being formed as an nFET with an N-channel inversion region at said second side of said fin structure.

15. The method of claim 13 , said FinFET being formed as a pFET with a P-channel inversion region at said first side of said fin structure.

16. The method of claim 13 , said channel region comprising silicon.

17. The method of claim 13 , said forming of said differently strained films comprising forming a tensile film on said second side of said fin structure and a relaxed film on said first side of said fin structure opposite said tensile film.

18. The method of claim 13 , further comprising forming an oxide cap layer over said fin structure.

19. The method of claim 13 , said forming of said differently strained films comprising:

forming a first film comprising nitride and having tensile stress on said second side of said fin structure;

releasing the tensile stress by introducing an angle implant to said first film; and

forming a second film comprising nitride and having compressive stress on said first side of said fin structure.

20. The method of claim 13 , said forming of said differently strained films comprising:

forming a first film comprising nitride and having a first type of stress on said fin structure;

damaging nitride on said fin structure by introducing an angle implant to said fin structure;

etching the damaged nitride; and

forming a second film comprising nitride and having a second type of stress on said fin structure,

wherein said first type of stress is mechanically opposite to said second type of stress.