Package structure in which coreless substrate has direct electrical connections to semiconductor chip and manufacturing method thereof
A package structure in which a coreless substrate has direct electrical connections to a semiconductor chip and a manufacturing method thereof are disclosed. The method includes the following steps: providing a metal carrier board having a cavity; placing a chip having a plurality of electrode pads on an active surface in the cavity of a board; filling the cavity with an adhesive for fixing the chip; forming a solder mask on the active surface of the chip and the surface of the metal carrier board at the same side, wherein the solder mask has a plurality of openings to expose the electrode pads of the chip; forming a built-up structure on the solder mask and the exposed active surface of the chip in the openings; and removing the metal carrier board. In this method the metal carrier board can support the built-up structure to thereby avoid warpage.
1. A package structure in which a coreless substrate has direct electrical connections to a semiconductor chip, comprising:
a semiconductor chip having an active surface and an opposite inactive surface, wherein the active surface has a plurality of electrode pads thereon;
a built-up structure having a first surface and an opposite second surface, wherein the built-up structure comprises at least one dielectric layer, at least one circuit layer stacked on the dielectric layer, and a plurality of conductive vias; the outermost circuit layer of the second surface of the built-up structure has a plurality of conductive pads;
a first solder mask, which has a plurality of openings corresponding to the electrode pads of the semiconductor chip, disposed on the first surface of the built-up structure, wherein parts of the conductive vias in the built-up structure each respectively penetrate and completely fill the first openings of the first solder mask, and electrically connect to and directly contact the electrode pads of the semiconductor chip; and
a second solder mask disposed on the second surface of the built-up structure, wherein the second solder mask has a plurality of second openings exposing the conductive pads of the built-up structure and an adhesive material wrapping and protecting the semiconductor chip, also enhancing the adhesion between the semiconductor chip and the built-up structure, therewith the inactive surface of the semiconductor chip is exposed to dissipate heat generated by the semiconductor chip during operation.
2. The structure as claimed in claim 1 , further comprising a metal supporting frame disposed on the first solder mask to thereby enhance the rigidity of the built-up structure.
3. A package structure in which a coreless substrate has direct electrical connections to a semiconductor chip, comprising:
a semiconductor chip having an active surface and an opposite inactive surface, wherein the active surface has a plurality of electrode pads thereon;
a built-up structure having a first surface and an opposite second surface, wherein the built-up structure comprises at least one dielectric layer, at least one circuit layer stacked on the dielectric layer, and a plurality of conductive vias; the outermost circuit layer of the second surface of the built-up structure has a plurality of conductive pads; and
a first solder mask, which has a plurality of openings corresponding to the electrode pads of the semiconductor chip, disposed on the first surface of the built-up structure, wherein parts of the conductive vias in the built-up structure each respectively penetrate and completely fill the first openings of the first solder mask, and electrically connect to and directly contact the electrode pads of the semiconductor chip and an adhesive material wrapping and protecting the semiconductor chip, also enhancing the adhesion between the semiconductor chip and the built-up structure, therewith the inactive surface of the semiconductor chip is exposed to dissipate heat generated by the semiconductor chip during operation.
4. A package structure in which a coreless substrate has direct electrical connections to a semiconductor chip, comprising:
a semiconductor chip having an active surface and an opposite inactive surface, wherein the active surface has a plurality of electrode pads thereon;
a built-up structure having a first surface and an opposite second surface, wherein the built-up structure comprises at least one dielectric layer, at least one circuit layer stacked on the dielectric layer, and a plurality of conductive vias; the outermost circuit layer of the second surface of the built-up structure has a plurality of conductive pads;
a first solder mask, which has a plurality of openings corresponding to the electrode pads of the semiconductor chip, disposed on the first surface of the built-up structure, wherein parts of the conductive vias in the built-up structure each respectively penetrate the first openings of the first solder mask, and electrically connect to the electrode pads of the semiconductor chip; and
a second solder mask disposed on the second surface of the built-up structure, wherein the second solder mask has a plurality of second openings exposing the conductive pads of the built-up structure and an adhesive material wrapping and protecting the semiconductor chip, also enhancing the adhesion between the semiconductor chip and the built-up structure, therewith the inactive surface of the semiconductor chip is exposed to dissipate heat generated by the semiconductor chip during operation.