Defect source analysis method, defect source analysis apparatus, and method of manufacturing semiconductor device
An inspecting method increases the accuracy of a DSA (Defect Source Analysis) for thereby increasing the yield of semiconductor devices which are manufactured. For performing a DSA using data of a defect inspecting process obtained when wiring patterns are formed on a wafer and data of a VC (Voltage Contrast) inspecting process performed after the wiring patterns are formed, a rectangular DSA area is established in relation to a wiring pattern in which a nonconductive area is detected, based on the shape of the wiring pattern. For example, if three defects are detected in the defect inspecting process, then it is possible to select only at least one of those defects which affects the wiring pattern in the DSA area. Since fabrication steps can appropriately be evaluated based on the selected defect, suitable actions may be taken for any problematic fabrication step based on the evaluation of the fabrication steps.
1. A defect source analysis method comprising:
storing a first result of a first inspection of a wafer, a second result of a second inspection of the wafer and data of a shape of a conductive pattern by a defect source analysis apparatus, the first inspection performed by a first inspecting apparatus before forming the conductive pattern on the wafer and the second inspection performed by a second inspecting apparatus after forming the conductive pattern on the wafer;
establishing a defect source analysis area based on the shape of the conductive pattern by the defect source analysis apparatus; and
comparing the first result and the second result with each other in the defect source analysis area by the defect source analysis apparatus; wherein:
the conductive pattern is an inspection pattern formed in a chip on the wafer and connected to the wafer, and is a combtoothed pattern including a plurality of sub-patterns arranged in one direction that are electrically connected to each other; and
the establishing includes establishing the defect source analysis area that includes only one sub-pattern among the plurality of sub-patterns, wherein the one sub-pattern has a nonconductive area determined from the second result of the second inspection among the plurality of sub-patterns.
2. The defect source analysis method according to claim 1 , wherein the defect source analysis area has a rectangular shape surrounding the part or whole of the conductive pattern.
3. The defect source analysis method according to claim 1 , wherein the establishing comprises:
establishing the defect source analysis area in view of a shape of another conductive pattern formed in the chip on the wafer together with the conductive pattern.
4. The defect source analysis method according to claim 3 , wherein the establishing comprises:
establishing the defect source analysis area, exclusive of the other conductive pattern.
5. The defect source analysis method according to claim 1 , wherein the first result comprises at least one physical inspection result obtained before forming the conductive pattern, and the second result comprises an electrical inspection result obtained after forming the conductive pattern.
6. The method according to claim 5 , wherein the nonconductive area is determined from the electrical inspection result.
7. A defect source analysis apparatus comprising:
a storage unit configured to store a first result of a first inspection of a wafer, a second result of a second inspection of the wafer and data of a shape of a conductive pattern, the first inspection performed by a first inspecting apparatus before forming the conductive pattern on the wafer and the second inspection performed by a second inspecting apparatus after forming the conductive pattern on the wafer;
a second unit configured to establish a defect source analysis area based on the shape of the conductive pattern stored in the storage unit; and
a third unit configured to compare the first result and the second result with each other in the defect source analysis area established by the second unit; wherein:
the conductive pattern is an inspection pattern formed in a chip on the wafer and connected to the wafer, and is a combtoothed pattern including a plurality of sub-patterns arranged in one direction that are electrically connected to each other; and
the second unit establishes the defect source analysis area that includes only one sub-pattern among the plurality of sub-patterns, wherein the one sub-pattern has a nonconductive area determined from the second result of the second inspection among the plurality of sub-patterns.
8. The defect source analysis apparatus according to claim 7 , wherein the defect source analysis area has a rectangular shape surrounding the part or whole of the conductive pattern.
9. The defect source analysis apparatus according to claim 7 , wherein the second unit establishes the defect source analysis area in view of a shape of another conductive pattern formed in the chip on the wafer together with the conductive pattern.
10. The defect source analysis apparatus according to claim 9 ,
wherein the second unit establishes the defect source analysis area, exclusive of the other conductive pattern.
11. A method of manufacturing a semiconductor device comprising:
inspecting a wafer by using a defect source analysis apparatus, the inspecting including:
storing a first result of a first inspection of a wafer, a second result of a second inspection of the wafer and data of a shape of a conductive pattern by a defect source analysis apparatus, the first inspection performed by a first inspecting apparatus before forming the conductive pattern on the wafer and the second inspection performed by a second inspecting apparatus after forming the conductive pattern on the wafer;
establishing a defect source analysis area based on the shape of the conductive pattern by the defect source analysis apparatus; and
comparing the first result and the second result with each other in the defect source analysis area by the defect source analysis apparatus; wherein:
the conductive pattern is an inspection pattern formed in a chip on the wafer and connected to the wafer, and is a combtoothed pattern including a plurality of sub-patterns arranged in one direction that are electrically connected to each other; and
the establishing includes establishing the defect source analysis area that includes only one sub-pattern among the plurality of sub-patterns, wherein the one sub-pattern has a nonconductive area determined from the second result of the second inspection among the plurality of sub-patterns.
12. The method of manufacturing a semiconductor device according to claim 11 , wherein the defect source analysis area has a rectangular shape surrounding the part or whole of the conductive pattern.
13. The method of manufacturing a semiconductor device according to claim 11 , wherein the establishing comprises:
establishing the defect source analysis area in view of a shape of another conductive pattern formed in the chip on the wafer together with the conductive pattern.
14. The method of manufacturing a semiconductor device according to claim 13 , wherein the establishing comprises:
establishing the defect source analysis area, exclusive of the other conductive pattern.
15. The method of manufacturing a semiconductor device according to claim 11 , wherein the first result comprises at least one physical inspection result obtained before forming the conductive pattern, and the second result comprises an electrical inspection result obtained after forming the conductive pattern.
16. The method of manufacturing a semiconductor device according to claim 15 , wherein the nonconductive area is determined from the electrical inspection result.