Structures for semiconductor structures with error detection and correction

1. A design structure, comprising a semiconductor structure in a format of a text file or a graphical representation of the semiconductor structure, the design structure stored in a machine readable physically tangible storage device, the design structure being a component of a system configured to design, manufacture, or test the semiconductor structure, the semiconductor structure comprising:

(a) a first semiconductor chip and a second semiconductor chip,

wherein the first semiconductor chip is on top of and bonded to the second semiconductor chip,

wherein the first semiconductor chip comprises a first electric node,

wherein the second semiconductor chip comprises a second electric node, and

wherein the second semiconductor chip further comprises a first comparing circuit; and

(b) a first coupling via electrically connecting the first electric node of the first semiconductor chip to the first comparing circuit of the second semiconductor chip, wherein the first comparing circuit is capable of:

(i) receiving an input signal from the first electric node indirectly through the first coupling via,

(ii) receiving an input signal from the second electric node directly, and

(iii) asserting a first mismatch signal in response to the input signals from the first and second electric nodes being different.

2. The design structure of claim 1 , wherein the semiconductor structure further comprises a second coupling via,

wherein the first semiconductor chip further comprises a third electric node,

wherein the second semiconductor chip further comprises a fourth electric node,

wherein the second semiconductor chip further comprises a second comparing circuit,

wherein the second coupling via electrically connects the fourth electric node of the first semiconductor chip to the second comparing circuit of the second semiconductor chip, and

wherein the second comparing circuit is capable of:

(i) receiving an input signal from the third electric node indirectly through the second coupling via,

(ii) receiving an input signal from the fourth electric node directly, and

(iii) asserting a second mismatch signal in response to the input signals from the third and fourth electric nodes being different.

3. The design structure of claim 2 ,

wherein the second semiconductor chip further comprises a transferring circuit, and

wherein the transferring circuit is capable of asserting a local error signal in response to either the first comparing circuit asserting the first mismatch signal or the second comparing circuit asserting the second mismatch signal.

4. The design structure of claim 3 ,

wherein the third electric node is an output of a third functional latch of the first semiconductor chip,

wherein the fourth electric node is an output of a fourth functional latch of the second semiconductor chip,

wherein the first comparing circuit comprises a first exclusive-NOR circuit,

wherein the second comparing circuit comprises a second exclusive-NOR circuit, and

wherein the transferring circuit comprises a NAND-circuit.

5. The design structure of claim 1 , wherein the semiconductor structure further comprises a third coupling via,

wherein the first semiconductor chip further comprises a fifth electric node,

wherein the second semiconductor chip further comprises a sixth electric node,

wherein the first semiconductor chip further comprises a third comparing circuit,

wherein the third coupling via electrically connects the sixth electric node of the second semiconductor chip to the third comparing circuit of the first semiconductor chip, and

wherein the third comparing circuit is capable of:

(i) receiving an input signal from the fifth electric node directly,

(ii) receiving an input signal from the sixth electric node indirectly through the third coupling via, and

(iii) asserting a third mismatch signal in response to the input signals from the fifth and sixth electric nodes being different.

6. The design structure of claim 5 ,

wherein the first electric node is an output of a first functional latch of the first semiconductor chip,

wherein the second electric node is an output of a second functional latch of the second semiconductor chip,

wherein the fifth electric node is an output of a fifth functional latch of the first semiconductor chip,

wherein the sixth electric node is an output of a sixth functional latch of the second semiconductor chip, and

wherein the third comparing circuit comprises a third exclusive-NOR circuit.

7. The design structure of claim 1 , wherein the semiconductor structure further comprises a fourth coupling via,

wherein the first semiconductor chip further comprises a fourth comparing circuit,

wherein the fourth coupling via electrically connects the second electric node of the second semiconductor chip to the fourth comparing circuit of the first semiconductor chip, and

wherein the fourth comparing circuit is capable of:

(i) receiving an input signal from the first electric node directly,

(ii) receiving an input signal from the second electric node indirectly through the fourth coupling via, and

(iii) asserting a fourth mismatch signal in response to the input signals from the first and second electric nodes being different.

8. The design structure of claim 7 ,

wherein the fourth comparing circuit comprises a fourth exclusive-NOR circuit.

9. The design structure of claim 1 , wherein the semiconductor structure further comprises a third semiconductor chip,

wherein the second semiconductor chip is on top of and bonded to the third semiconductor chip, and

wherein the third semiconductor chip includes a seventh electric node.

10. The design structure of claim 9 ,

wherein the second semiconductor chip further comprises a voting logic electrically coupled to the first electric node, the second electric node, and the seventh electric node, and

wherein the voting logic is capable of outputting a majority signal of three signals on the first electric node, the second electric node, and the seventh electric node.

11. The design structure of claim 9 ,

wherein the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are functionally identical, and

wherein the seventh electric node is an output of a seventh functional latch of the third semiconductor chip.

12. The design structure of claim 1 , wherein the design structure comprises a netlist.

13. The design structure of claim 1 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

14. A design structure comprising a semiconductor structure in a format of a text file or a graphical representation of the semiconductor structure, the design structure stored in a machine readable physically tangible storage device, the design structure being a component of a system configured to design, manufacture, or test the semiconductor structure, the semiconductor structure comprising:

(a) a first semiconductor chip, a second semiconductor chip, and a first error checking layer,

wherein the first error checking layer is sandwiched between and bonded to the first and second semiconductor chips,

wherein the first semiconductor chip comprises a first electric node,

wherein the second semiconductor chip comprises a second electric node, wherein

the first error checking layer comprises a first comparing circuit;

(b) a first coupling via electrically connecting the first electric node of the first semiconductor chip to the first comparing circuit of the first error checking layer; and

(c) a second coupling via electrically connecting the second electric node of the second semiconductor chip to the first comparing circuit of the first error checking layer,

wherein the first comparing circuit is capable of:

(i) receiving an input signal from the first electric node indirectly through the first coupling via,

(ii) receiving an input signal from the second electric node indirectly through the second coupling via, and

(iii) asserting a first mismatch signal in response to the input signals from the first and second electric nodes being different.

15. The design structure of claim 14 , wherein the semiconductor structure further comprises a third coupling via and a fourth coupling via,

wherein the first semiconductor chip further comprises a third electric node,

wherein the second semiconductor chip further comprises a fourth electric node,

wherein the first error checking layer further comprises a second comparing circuit,

wherein the third coupling via electrically connects the third electric node of the third semiconductor chip to the second comparing circuit of the first error checking layer,

wherein the fourth coupling via electrically connects the fourth electric node of the second semiconductor chip to the second comparing circuit of the first error checking layer, and

wherein the second comparing circuit is capable of:

(i) receiving an input signal from the third electric node indirectly through the third coupling via,

(ii) receiving an input signal from the fourth electric node indirectly through the fourth coupling via, and

(iii) asserting a second mismatch signal in response to the input signals from the third and fourth electric nodes being different.

16. The design structure of claim 15 ,

wherein the first electric node is an output of a first functional latch of the first semiconductor chip,

wherein the second electric node is an output of a second functional latch of the second semiconductor chip,

wherein the third electric node is an output of a third functional latch of the first semiconductor chip,

wherein the fourth electric node is an output of a fourth functional latch of the second semiconductor chip,

wherein the first comparing circuit comprises a first exclusive-NOR circuit, and

wherein the second comparing circuit comprises a second exclusive-NOR circuit.

17. The design structure of claim 15 , wherein the semiconductor structure further comprises a transferring circuit, wherein the transferring circuit is capable of asserting a local error signal in response to either the first comparing circuit asserting the first mismatch signal or the second comparing circuit asserting the second mismatch signal.

18. The design structure of claim 14 , wherein the semiconductor structure further comprises a third semiconductor chip and a second error checking layer,

wherein the second error checking layer is sandwiched between and bonded to the second and third semiconductor chips,

wherein the third semiconductor chip further comprises a fifth electric node,

wherein the first error checking layer further comprises a voting logic electrically coupled to the first electric node, the second electric node, and the fifth electric node, and

wherein the voting logic is capable of outputting a majority signal of three signals on the first electric node, the second electric node, and the fifth electric node.

19. The design structure of claim 14 , wherein the design structure comprises a netlist.

20. The design structure of claim 14 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.