Non-volatile memory and method for power-saving multi-pass sensing
A non-volatile memory device and power-saving techniques capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during sensing, which is included in read, and program/verify operations. A sensing verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, coupling of the memory cells to their bit lines are delayed during a precharge operation in order to reduced the cells' currents working against the precharge. In another aspect, a power-consuming precharge period is minimized by preemptively starting the sensing in a multi-pass sensing operation. High current cells not detected as a result of the premature sensing will be detected in a subsequent pass.
1. A method of sensing a group of nonvolatile memory cells in parallel, comprising:
accessing individual memory cells by associated bit lines;
initially precharging the associated bit lines without coupling to the group of memory cells until the associated bit lines have substantially reached a first predetermined voltage;
continuing precharging the associated bit lines with the group of memory cells coupled thereto until the associated bit lines have substantially reached a second predetermined voltage that is stable for sensing; and
sensing the group of memory cells in parallel while coupled to the associated bit lines.
2. The method as in claim 1 , further comprising:
accessing individual memory cells by a word line;
selecting a demarcation threshold voltage relative to which the sensing is to be performed; and
precharging the word line to the selected demarcation threshold voltage.
3. The method as in claim 1 , wherein said sensing is a part of a read operation to read the memory states programmed into said group of memory cells.
4. The method as in claim 1 , wherein said sensing is a part of a program operation to verify if any of the memory cells has been programmed relative to the selected demarcation threshold voltage.
5. The method as in claim 1 , wherein the group of nonvolatile memory cells are portion of a flash EEPROM.
6. The method as in claim 1 , wherein the nonvolatile memory cell of the group stores one bit of data.
7. The method as in claim 1 , wherein the nonvolatile memory cell of the group stores more than one bit of data.
8. The method as in claim 2 , wherein the nonvolatile memory cell of the group stores one bit of data.
9. The method as in claim 2 , wherein the nonvolatile memory cell of the group stores more than one bit of data.
10. The method as in claim 3 , wherein the nonvolatile memory cell of the group stores one bit of data.
11. The method as in claim 3 , wherein the nonvolatile memory cell of the group stores more than one bit of data.
12. The method as in claim 4 , wherein the nonvolatile memory cell of the group stores one bit of data.
13. The method as in claim 4 , wherein the nonvolatile memory cell of the group stores more than one bit of data.
14. The method as in claim 5 , wherein the nonvolatile memory cell of the group stores one bit of data.
15. The method as in claim 5 , wherein the nonvolatile memory cell of the group stores more than one bit of data.