Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods

1. A semiconductor device comprising:

a semiconductor substrate having an active region and a shallow trench isolation region having a divot;

an epitaxial layer on the active region of the semiconductor substrate with a lateral overhang portion in the divot at an interface of the active region and the shallow trench isolation region; and

a first gate stack-forming layer overlying the semiconductor substrate and comprising a non-conformal layer of metal gate-forming material having a thinned break portion just below the lateral overhang portion, wherein a first portion of the non-conformal layer of metal gate-forming material is in a gate stack and a second portion is exposed with the thinned break portion at least partially isolating the first and second portions.

2. The semiconductor device of claim 1 , wherein the active region comprises a pFET active region and the epitaxial layer comprises a channel Silicon Germanium (cSiGe) epitaxial layer.

3. The semiconductor device of claim 2 , wherein the cSiGe epitaxial layer comprises about 15 to about 40 atomic percent germanium.

4. The semiconductor device of claim 1 , wherein the active region comprises an nFET active region and the epitaxial layer comprises a silicon epitaxial layer.

5. The semiconductor device of claim 1 , wherein the gate stack further comprises a substantially etch resistant gate insulator material and the first portion of the non-conformal layer of metal gate-forming material overlies the gate insulator material.

6. The semiconductor device of claim 5 , wherein the metal gate-forming material is selected from the group consisting of lanthanum, lanthanum alloys, aluminum, aluminum alloys, magnesium, magnesium alloys, titanium-based materials, and tantalum-based materials.

7. The semiconductor device of claim 1 , wherein the gate stack further comprises a second gate stack-forming layer overlying the first gate stack-forming layer, wherein the second gate stack-forming layer has a composition different from the first gate stack-forming layer.

8. The semiconductor device of claim 7 , wherein the second gate stack-forming layer comprises polycrystalline or amorphous silicon.

9. A semiconductor transistor device comprising:

a semiconductor substrate having an active region and a shallow trench isolation region having a divot;

an epitaxial layer on the active region with a lateral overhang portion at an interface of the active region and the shallow trench isolation region;

a gate stack overlying the semiconductor substrate, the gate stack comprising:

a conformal gate insulator on the epitaxial layer including on the lateral overhang portion, the conformal gate insulator also within the divot;

a non-conformal metal gate-forming material on the conformal gate insulator, the non-conformal metal gate-forming material also within the divot, wherein the non-conformal metal gate-forming material has a thinned break portion under the lateral overhang portion, and wherein the conformal gate insulator and the non-conformal metal gate-forming material form a first gate stack-forming layer; and

a second gate stack-forming layer overlying the first gate stack-forming layer in the gate stack and also within the divot; and

sidewall spacers abutting sidewalls of the gate stack, wherein the sidewall spacers cover a first portion of the first gate stack-forming layer in the divot leaving a second portion exposed.

10. The semiconductor transistor device of claim 9 , wherein the active region comprises a pFET active region and the epitaxial layer comprises a channel Silicon Germanium (cSiGe) epitaxial layer.

11. The semiconductor device of claim 10 , wherein the cSiGe epitaxial layer comprises about 15 to about 40 atomic percent germanium.

12. The semiconductor transistor device of claim 9 , wherein the active region comprises an nFET active region and the epitaxial layer comprises a silicon epitaxial layer.

13. The semiconductor transistor device of claim 9 , wherein the conformal gate insulator comprises silicon dioxide, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric.

14. The semiconductor transistor device of claim 9 , wherein the conformal gate insulator is substantially etch-resistant to wet etch chemistries using sulfur peroxide, ammonium peroxide, or hydrofluoric acid.

15. The semiconductor transistor device of claim 9 , wherein the thinned break portion is between the non-conformal metal gate-forming material within the divot and the non-conformal metal gate-forming material in the gate stack.

16. The semiconductor transistor device of claim 15 , wherein a thickness of the non-conformal metal gate-forming material at the thinned break portion is between about 0 nm to about 1 nm.

17. The semiconductor transistor device of claim 9 , wherein the non-conformal metal gate-forming material is selected from the group consisting of lanthanum, lanthanum alloys, aluminum, aluminum alloys, magnesium, magnesium alloys, titanium-based materials, and tantalum-based materials.

18. The semiconductor transistor device of claim 9 , wherein the second gate stack-forming layer has a composition different from the first gate stack-forming layer.

19. The semiconductor transistor device of claim 18 , wherein the second gate stack-forming layer comprises polycrystalline or amorphous silicon.

20. The semiconductor transistor device of claim 9 , wherein the sidewall spacers have a thickness in the range of about 2 nm to about 9 nm.