IP Library Granted Patent US 8,268,727
Granted Patent B2
US 8,268,727 · App. 12/426,827 · Granted Sep 18, 2012

Methods for fabricating FinFET semiconductor devices using planarized spacers

Assignee: GLOBALFOUNDRIES, Inc.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,268,727
App. No.
12/426,827
Granted
Sep 18, 2012
Kind
B2
Abstract

Methods of fabricating a semiconductor device on and in a semiconductor substrate are provided. In accordance with an exemplary embodiment of the invention, one method comprises forming a sacrificial mandrel overlying the substrate, wherein the sacrificial mandrel has sidewalls. Sidewall spacers are formed adjacent the sidewalls of the sacrificial mandrel, the sidewall spacers having an upper portion and a lower portion. The upper portion of the sidewall spacers is removed. The sacrificial mandrel is removed and the semiconductor substrate is etched using the lower portion of the sidewall spacers as an etch mask.

Claims (48)

1. A method of fabricating a semiconductor device on and in a semiconductor substrate, the method comprising the steps of:

forming a sacrificial mandrel overlying the substrate, the sacrificial mandrel having sidewalls;

forming sidewall spacers adjacent the sidewalls of the sacrificial mandrel, the sidewall spacers having a rounded and sloping upper portion and a lower portion having a substantially rectangular cross-sectional shape;

removing the upper portion of the sidewall spacers to leave only the lower portion of the sidewall spacers having the substantially rectangular shape;

removing the sacrificial mandrel; and

etching the semiconductor substrate using the lower portion of the sidewall spacers as an etch mask.

2. The method of claim 1 , wherein the step of removing the upper portion comprises removing the upper portion using a CMP process.

3. The method of claim 1 , wherein the step of removing the upper portion comprises removing the upper portion using an etch process.

4. The method of claim 1 , wherein the sidewall spacers and the sacrificial mandrel have a first thickness, further comprising the step of:

depositing a planarizing layer overlying the substrate, the sacrificial mandrel, and the sidewall spacers, the planarizing layer having a second thickness greater than the first thickness; and

etching the planarizing layer back to substantially the first thickness.

5. The method of claim 4 , further comprising the step of etching the planarizing layer, the upper portion of the sidewall spacers, and the sacrificial mandrel at substantially the same rate.

6. The method of claim 4 , further comprising the step of removing the planarizing layer.

7. The method of claim 4 , wherein the step of depositing a planarizing layer comprises depositing a silicon-comprising planarizing layer.

8. The method of claim 4 , wherein the step of forming a sacrificial mandrel comprises:

forming a first mandrel layer overlying the substrate;

forming a second mandrel layer overlying the first mandrel layer, wherein the first and second mandrel layers have different compositions; and

etching the first and second mandrel layers to form the sacrificial mandrel.

9. The method of claim 8 , wherein the step of forming sidewall spacers and the step of forming a second mandrel layer comprise forming sidewall spacers and forming a second mandrel layer having the same composition.

10. The method of claim 8 , further comprising the step of etching the planarizing layer, the upper portion of the sidewall spacers, and the second mandrel layer at substantially the same rate.

11. The method of claim 10 , wherein the step of etching the planarizing layer, the upper portion of the sidewall spacers, and the second mandrel layer further comprises etching the planarizing layer, the upper portion of the sidewall spacers, and the second mandrel layer selectively from the first mandrel layer.

12. A method of fabricating a semiconductor device on and in a semiconductor substrate, the method comprising the steps of:

forming a sacrificial mandrel overlying the substrate, the sacrificial mandrel having sidewalls;

forming sidewall spacers adjacent the sidewalls of the sacrificial mandrel, the sidewall spacers having a rounded and sloping upper portion and a lower portion having a substantially rectangular cross-sectional shape;

reducing the aspect ratio of the sidewall spacers with a chemical mechanical planarization process that removes the upper portion to leave only the lower portion of the sidewall spacers having the substantially rectangular shape;

removing the sacrificial mandrel; and

etching the semiconductor substrate using the lower portion of the sidewall spacers as an etch mask.

13. The method of claim 12 , wherein the step of forming a sacrificial mandrel comprises:

forming a first mandrel layer overlying the substrate;

forming a second mandrel layer overlying the first mandrel layer, wherein the first and second mandrel layers have different compositions; and

etching the first and second mandrel layers to form the sacrificial mandrel.

14. The method of claim 13 , wherein the step of reducing comprises the step of removing the second mandrel layer selectively from the first mandrel layer.

15. The method of claim 13 , wherein the step of forming sidewall spacers and the step of forming a second mandrel layer comprise forming sidewall spacers and forming a second mandrel layer having the same composition.

16. A method of fabricating a semiconductor device on and in a semiconductor substrate, the substrate having a surface, the method comprising the steps of:

forming a sacrificial mandrel overlying the surface of the substrate, the sacrificial mandrel having sidewalls;

forming sidewall spacers adjacent the sidewalls of the sacrificial mandrel, the sidewall spacers having a rounded and sloping upper portion and a lower portion having a substantially rectangular cross-sectional shape;

depositing a planarizing layer overlying the surface of the substrate, the sacrificial mandrel, and the sidewall spacers;

etching the sacrificial mandrel, the sidewall spacers, and the planarizing layer at substantially the same rate until the upper portion of the sidewall spacers is removed to leave only the lower portion of the sidewall spacers having the substantially rectangular shape;

removing the planarizing layer;

removing the sacrificial mandrel; and

etching the semiconductor substrate using the lower portion of the sidewall spacers as an etch mask.

17. The method of claim 16 , wherein the step of depositing a planarizing layer comprises depositing a silicon-comprising planarizing layer.

18. The method of claim 16 , wherein the step of forming a sacrificial mandrel comprises:

forming a first mandrel layer overlying the substrate;

forming a second mandrel layer overlying the first mandrel layer, wherein the first and second mandrel layers have different compositions; and

etching the first and second mandrel layers to form the sacrificial mandrel.

19. The method of claim 18 , wherein the step of etching the sacrificial mandrel comprises etching the sacrificial mandrel until the upper portion is removed and such that the second mandrel layer is selectively removed from the first mandrel layer.

20. The method of claim 18 , wherein the step of forming sidewall spacers and the step of forming a second mandrel layer comprise forming sidewall spacers and forming a second mandrel layer having the same composition.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR ON LAST PARAGRAPH OF THE FIRST PAGE PREVIOUSLY RECORDED ON REEL 022843 FRAME 0379. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE "ADVANCED MICRO DEVICES, INC." TO "GLOBALFOUNDRIES INC.". Recorded Jul 29, 2009
From: JOHNSON, FRANK S.; BONSER, DOUGLAS
To: GLOBALFOUNDRIES INC.
Reel/Frame 023024/0913 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2009
From: JOHNSON, FRANK S.; BONSER, DOUGLAS
To: GLOBALFOUNDRIES INC.
Reel/Frame 022843/0379 →
Continuity (1)
Related Publication 20100267238A1 · Oct 21, 2010