Electronic device including a buried insulating layer and a vertical conductive structure extending therethrough and a process of forming the same
An electronic device can include a buried conductive region, a buried insulating layer over the buried conductive region, and a semiconductor layer disposed over the buried insulating layer, wherein the semiconductor layer has a primary surface and an opposing surface, and the buried conductive region is disposed closer to the opposing surface than to the primary surface. The electronic device can also include a current-carrying electrode of a first transistor, wherein the current carrying electrode is disposed along the primary surface and spaced apart from the buried conductive layer. The electronic device can also include a vertical conductive structure extending through the buried insulating layer, wherein the vertical conductive structure is electrically connected to the current-carrying electrode and the buried conductive region.
1. An electronic device comprising:
a buried conductive region;
a buried insulating layer over the buried conductive region;
a semiconductor layer disposed over the buried insulating layer, wherein the semiconductor layer has a primary surface and an opposing surface, and the buried conductive region is disposed closer to the opposing surface than to the primary surface;
a first current-carrying electrode of a first transistor, wherein the first current carrying electrode is disposed along the primary surface and spaced apart from the buried conductive layer; and
a first vertical conductive structure extending through the buried insulating layer, wherein the first vertical conductive structure is electrically connected to the first current-carrying electrode and the buried conductive region, wherein the first vertical conductive structure defines a void disposed adjacent to the buried insulating layer, wherein substantially all of the void is disposed at an elevation that is spaced apart from an elevation of the primary surface.
2. The electronic device of claim 1 , wherein the first vertical conductive structure extends at least approximately 0.2 micron into the buried conductive region.
3. The electronic device of claim 1 , wherein the first current-carrying electrode is a source region.
4. The electronic device of claim 1 , wherein:
the buried conductive region has a first dopant concentration at a first location and a second dopant concentration at a second location;
the buried insulating layer is closer to the first location than the second location; and
the first dopant concentration is less than the second dopant concentration.
5. The electronic device of claim 4 , wherein the buried conductive region has a third dopant concentration at a third location, wherein:
the buried insulating layer is closest to the third location than to the first and second locations; and
the third dopant concentration is greater than the first dopant concentration and less than the second dopant concentration.
6. The electronic device of claim 5 , wherein the buried conductive region is n-type doped.
7. The electronic device of claim 1 , wherein the first current carrying electrode is a drain region.
8. The electronic device of claim 1 , further comprising:
a second current-carrying electrode of a second transistor, wherein the second current carrying electrode is disposed along the primary surface and spaced apart from the buried conductive layer; and
a second vertical conductive structure extending through the buried insulating layer, wherein the second vertical conductive region is electrically connected to the second current-carrying electrode and the buried conductive region.
9. The electronic device of claim 8 , wherein the first current-carrying electrode is a drain region of the first transistor, and the second current-carrying electrode is a source region of the second transistor.
10. The electronic device of claim 8 , wherein the first and second transistors are both n-channel power transistors or both p-channel power transistors.
11. The electronic device of claim 8 , wherein the first transistor is a low-side transistor of a power switching circuit and the second transistor is a high-side transistor of the power switching circuit.
12. The electronic device of claim 8 , wherein:
the first transistor comprises a first control electrode;
the second transistor comprises a second control electrode; and
the electronic device further comprises:
a first control terminal coupled to the first control electrode; and
a second control terminal coupled to the second control electrode.
13. An electronic device comprising:
a buried conductive region;
a buried insulating layer over the buried conductive region;
a semiconductor layer disposed over the buried insulating layer, wherein the semiconductor layer has a primary surface and an opposing surface, and the buried conductive region is disposed closer to the opposing surface than to the primary surface;
a first current-carrying electrode of a first transistor, wherein the first current carrying electrode is disposed along the primary surface and spaced apart from the buried conductive layer;
a first vertical conductive structure extending through the buried insulating layer, wherein the first vertical conductive structure is electrically connected to the first current-carrying electrode and the buried conductive region; and
an insulating liner disposed between the first vertical conductive structure and the semiconductor layer.
14. A process of forming an electronic device comprising:
providing a substrate that includes a semiconductor layer over a buried insulating layer that is over a buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface, and the buried conductive region is disposed closer to the opposing surface than to the primary surface;
forming a first doped region within the semiconductor layer and along the primary surface of the first semiconductor layer, wherein the first doped region is part of a first current-carrying electrode of a first transistor; and
forming a first vertical conductive structure extending through at least part of the semiconductor layer and buried insulating layer, wherein, in a finished device, the buried conductive region, the first vertical conductive structure, and the first doped region are electrically connected to one another;
forming a second doped region within the semiconductor layer and along the primary surface of the semiconductor layer, wherein the second doped region is part of a second current-carrying electrode of a second transistor; and
forming a second vertical conductive structure extending through at least part of the semiconductor layer and buried insulating layer, wherein, in a finished device, the buried conductive region, the second vertical conductive structure, and the second doped region are electrically connected to one another.
15. The process of claim 14 , further comprising forming a trench extending through the first semiconductor layer and the buried insulating layer.
16. The process of claim 15 , wherein forming the first vertical conductive structure comprises depositing a conductive material within the trench.
17. The process of claim 15 , further comprising thermally oxidizing a part of the semiconductor layer along a wall of the trench before depositing the conductive material.
18. The process of claim 17 , further comprising extending the trench to a depth of at least 0.2 micron into the buried conductive region, wherein extending the trench is performed after thermally oxidizing the part of the semiconductor layer and before depositing the conductive material.
19. The process of claim 14 , wherein the first current-carrying electrode is a drain region of the first transistor, and the second current-carrying electrode is a source region of the second transistor.
20. The process of claim 14 , wherein:
forming the second doped region is performed after forming the second vertical conductive structure;
forming the first conductive structure and forming the second conductive structure are performed during substantially a same time period; and
forming the first conductive structure is performed before forming the first doped region.
21. The process of claim 14 , wherein the first vertical conductive structure comprises a heavily doped semiconductor material.