Data processing system having bit exact instructions and methods therefor
A method for operating a data processing system is provided. The method includes providing a first operand stored in a first register, providing a second operand stored in the register, providing a third operand stored in the register. The method further includes executing a first instruction, where executing the first instruction comprises: (1) retrieving the first operand, the second operand, and the third operand from the first register; (2) performing an operation using the first operand, the second operand, and the third operand to generate a bit exact result.
1. A data processing system, comprising:
means for storing a first portion of an instruction, wherein the first portion of the instruction selects a vector operation;
means for storing a second portion of the instruction, wherein the second portion of the instruction selects operand width used in the vector operation;
means for storing a third portion of the instruction, wherein the third portion of the instruction selects one of an addition operation and a subtraction operation to be used in the vector operation;
means for storing a fourth portion of the instruction, wherein the fourth portion of the instruction selects signed or unsigned for the vector operation;
means for storing a fifth portion of the instruction, wherein the fifth portion of the instruction selects saturated or unsaturated for the vector operation;
means for storing a sixth portion of the instruction, wherein the sixth portion of the instruction selects fractional or integer for the vector operation;
means for storing a seventh portion of the instruction, wherein the seventh portion of the instruction selects one or more of an upper portion of a destination register and a lower portion of the destination register for storing a bit exact result of the vector operation;
means for storing a eighth portion of the instruction, wherein the eighth portion of the instruction selects a width of the bit exact result of the vector operation; and
means for storing a ninth portion of the instruction, wherein the ninth portion of the instruction selects a whether the bit exact result is stored in an accumulator as well as in the destination register.
2. A data processing system as in claim 1 , wherein if the ninth portion of the instruction selects that the bit exact result is to be stored in an accumulator as well as in the destination register, then the seventh portion of the instruction also selects one or more of an upper portion of the accumulator and a lower portion of the accumulator for storing the bit exact result of the vector operation.
3. A method for operating a data processing system, comprising:
executing a single instruction to perform a vector dot product, wherein executing the single instruction to perform the vector dot product comprises:
retrieving a first portion of a first vector, a second portion of the first vector, and a third portion of the first vector from a first register;
retrieving a first portion of a second vector, a second portion of the second vector, and a third portion of the second vector from a second register;
multiplying the first portion of the first vector and the first portion of the second vector to produce a first intermediate product;
multiplying the second portion of the first vector and the second portion of the second vector to produce a second intermediate product;
multiplying the third portion of the first vector and the third portion of the second vector to produce a third intermediate product;
selecting an operation to perform;
prior to performing the operation using the first intermediate product, the second intermediate product, and the third intermediate product to produce a result,
wherein the result is a bit exact result, saturating the first intermediate product, if the first intermediate product overflowed or underflowed, concurrently saturating the second intermediate product, if the second intermediate product overflowed or underflowed and concurrently saturating the third intermediate product, if the third intermediate product overflowed or underflowed.