Method and apparatus for sending data from multiple sources over a communications bus
In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed.
1. An electronic system comprising:
a processor, which generates and sends one or more memory access requests; and
multiple memory modules, operatively coupled together through a communications bus, which return data requested in the one or more memory access requests, wherein each of the multiple memory modules is a data source, and a memory module of the multiple memory modules is configured to:
determine that first source data and second source data are available,
allocate one or more first contiguous lanes within a first section of a data block to at least some of the first source data, wherein the data block comprises a set of multiple lanes, and each lane includes a set of configurable bits,
allocate one or more second contiguous lanes within a second section of the data block to at least some of the second source data, wherein the second section begins at a next lane, which is contiguous with the first section,
send over the communications bus and during a data block transmission period, the at least a portion of the first source data within the first section of the data block, and the at least a portion of the second source data within the second section of the data block;
receive downstream data from a second memory module over the communications bus, wherein the downstream data is a selected one of the first source data and the second source data;
receive local data from one or more memory storage units accessible to the memory module, wherein the local data is the selected one of the first source data and the second source data; and
assemble the downstream data and the local data into the data block.
2. The electronic system of claim 1 , further comprising:
a link controller, operatively coupled between the processor and to at least one of the multiple memory modules, the link controller configured to receive the one or more memory access requests, and to generate and send one or more memory access commands, based on the one or more memory access requests, to the multiple memory modules over the communications bus.
3. The electronic system of claim 1 , further comprising:
the communications bus having a first part and a second part, the first part to convey data to one of the memory modules from one or more other ones of the memory modules in a downstream direction, and the second part to convey the at least a portion of the first source data and the at least a portion of the second source data from the one of the memory modules to the link controller.
4. The electronic system of claim 1 , wherein the memory module comprises:
means for receiving downstream data from the second memory module over the communications bus, wherein the downstream data is the first source data;
means for receiving local data from one or more memory storage units accessible to the memory module, wherein the local data is the second source data; and
means for assembling the downstream data and the local data into the data block.
5. The electronic system of claim 1 , wherein the memory module comprises:
means for receiving downstream data from the second memory module over the communications bus, wherein the downstream data is the second source data;
means for receiving local data from one or more memory storage units accessible to the memory module, wherein the local data is the first source data; and
means for assembling the downstream data and the local data into the data block.
6. The electronic system of claim 1 , wherein the electronic system comprises a computer.
7. A memory module comprising:
one or more memory storage units for storing local data; and
a hub, operatively coupled to the one or more memory storage units and to a communications bus over which the hub can receive downstream data from one or more other hubs, wherein the hub is configured to:
determine that first source data and second source data are available,
allocate one or more first contiguous lanes within a first section of a data block to at least some of the first source data, wherein the data block comprises a set of multiple lanes, and each lane includes a set of configurable bits,
allocate one or more second contiguous lanes within a second section of the data block to at least some of the second source data, wherein the second section begins at a next lane, which is contiguous with the first section,
send over the communications bus and during a data block transmission period, the at least a portion of the first source data within the first section of the data block, and the at least a portion of the second source data within the second section of the data block;
receive the downstream data from a second hub over the communications bus, wherein the downstream data is a selected one of the first source data and the second source data;
receive the local data from the one or more memory storage units, wherein the local data is the selected one of the first source data and the second source data; and
assemble the downstream data and the local data into the data block.
8. The memory module of claim 7 , wherein the one or more memory storage units and the hub are co-located on a single substrate that is removably connectable to the communications bus.
9. The memory module of claim 7 , wherein the one or more memory storage units includes one or more random access memory components.
10. The memory module of claim 9 , wherein the one or more random access memory components includes one or more dynamic read only memory components.
11. The memory module of claim 7 , wherein the one or more memory storage units includes one or more read only memory components.
12. The memory module of claim 7 , wherein the hub includes one or more application specific integrated circuits.
13. The memory module of claim 7 , wherein the hub is configured to receive local data and downstream data.
14. The memory module of claim 7 , wherein the hub is configured to determine how data from different sources is to be merged together into merged data, and to provide the merged data to an upstream link bus.
15. The memory module of claim 7 , wherein the hub is configured to communicate over an upstream link bus to upstream memory modules.
16. The memory module of claim 7 , wherein the hub is configured to communicate to a link controller.
17. The memory module of claim 7 , wherein the hub comprises:
means for receiving the downstream data from the second hub over the communications bus, wherein the downstream data is the first source data;
means for receiving the local data from the one or more memory storage units, wherein the local data is the second source data; and
means for assembling the downstream data and the local data into the data block.
18. An apparatus for assembling and sending data, the apparatus comprising a module configured to:
receive local data from one or more memory storage units;
receive downstream data over a communications bus from one or more downstream data sources;
generate a first access request to send the local data over the communications bus;
generate a second access request to send the downstream data over the communications bus,
make a determination of how the local data and the downstream data will be sent over the communications bus, including configuration to:
receive the first access request and the second access request, and base the determination on the first access request and the second access request;
allocate one or more first contiguous lanes within a first section of a data block to at least some of the local data, wherein the data block comprises a set of multiple lanes, and each lane of the set includes a set of configurable bits,
allocate one or more second contiguous lanes within a second section of the data block to at least some of the downstream data, wherein the first section and the second section are contiguous;
arrange the local data and the downstream data into the data block, according to the determination; and
send the data within the data block over the communications bus during a data block transmission period.
19. The apparatus of claim 18 , wherein a hub is used to make the determination of how the local data and the downstream data will be sent over the communications bus.
20. The apparatus of claim 19 , wherein the hub comprises a local data buffer and a downstream data buffer.