Transistor device comprising an embedded semiconductor alloy having an asymmetric configuration

1. A method, comprising:

forming a gate electrode structure above a crystalline semiconductor region;

after forming said gate electrode structure, forming a semiconductor alloy in cavities formed in said crystalline semiconductor region, said cavities being laterally offset from a channel region of a transistor, said semiconductor alloy inducing strain in said channel region; and

selectively introducing a non-doping species into said semiconductor alloy positioned at a drain side of said transistor to reduce an internal strain level of said semiconductor alloy positioned at said drain side.

2. The method of claim 1 , wherein selectively introducing said non-doping species comprises forming an implantation mask to cover a source side and expose said drain side and performing an implantation process on the basis of said implantation mask.

3. The method of claim 1 , wherein said non-doping species comprises at least one of silicon, xenon, argon and fluorine.

4. The method of claim 3 , wherein the ion implantation process is performed on the basis of a dopant species.

5. The method of claim 1 , further comprising forming a drain region at least partially in said semiconductor alloy of reduced internal strain level and forming a source region at least partially in said semiconductor alloy positioned at said source side.

6. The method of claim 1 , wherein said semiconductor alloy comprises at least one of germanium and tin.

7. A method of forming an asymmetric transistor, the method comprising:

forming a gate electrode structure above a semiconductor region;

after forming said gate electrode structure, forming a source side cavity in said semiconductor region, said source side cavity being positioned laterally offset from a channel region located below said gate electrode structure of said transistor; and

forming a strain-inducing semiconductor alloy in said source side cavity, said strain-inducing semiconductor alloy representing an asymmetric transistor configuration of a source side relative to a drain side of said transistor, wherein the asymmetric transistor configuration comprises at least one of a dopant profile and a dopant concentration.

8. The method of claim 7 , wherein forming said source side cavity comprises forming an etch mask that covers said drain side and exposes said source side and performing an etch process on the basis of said etch mask.

9. The method of claim 8 , wherein forming said etch mask comprises depositing a spacer layer above said gate electrode structure, forming a resist mask above said drain side and patterning said spacer layer on the basis of said resist mask.

10. The method of claim 9 , wherein said spacer layer and said resist mask are formed so as to cover a second transistor.

11. The method of claim 9 , wherein forming said semiconductor alloy comprises performing a selective epitaxial growth process and using said patterned spacer layer as a deposition mask.

12. The method of claim 7 , further comprising forming a drain side cavity and forming a semiconductor material in said drain side cavity.

13. The method of claim 12 , wherein said source side cavity and said drain side cavity are formed in a common etch process.

14. The method of claim 12 , wherein forming said strain-inducing semiconductor alloy and said semiconductor material comprises forming a first deposition mask in one of said drain side cavity and said source cavity and performing a first selective epitaxial growth process to grow one of said strain-inducing semiconductor alloy and said semiconductor material.

15. The method of claim 14 , further comprising forming a second deposition mask on said one of said strain-inducing semiconductor alloy and said semiconductor material, removing said first deposition mask and growing the other one of said strain-inducing semiconductor alloy and said semiconductor material.

16. The method of claim 12 , wherein said semiconductor material differs from said strain-inducing semiconductor alloy in at least one of a material composition and an internal dopant concentration.

17. The method of claim 16 , wherein said semiconductor material induces strain in said channel region.

18. An asymmetric transistor, comprising:

a gate electrode structure formed above a channel region;

a source region formed at a source side of a semiconductor region of said transistor;

a strain-inducing semiconductor alloy formed at said source side; and

a drain region formed at a drain side of said semiconductor region, said drain side differing from said source side in an amount of strain induced in said channel region and in at least one of a dopant profile and a dopant concentration.

19. The asymmetric transistor of claim 18 , further comprising at least one of:

wherein said drain side comprises a semiconductor alloy and a non-doping species; and

wherein said drain side differs from said source side in material composition.

20. The asymmetric transistor of claim 19 , wherein said semiconductor alloy is in a substantially relaxed state.

21. The asymmetric transistor of claim 18 , wherein said strain-inducing semiconductor alloy is exclusively positioned at said source side.

22. The asymmetric transistor of claim 18 , further comprising a second semiconductor alloy formed at said drain side, wherein said strain-inducing semiconductor alloy differs from said second semiconductor alloy in at least a dopant concentration and a material composition.

23. The asymmetric transistor of claim 22 , wherein said second semiconductor alloy is provided in a lesser strained state compared to said strain-inducing semiconductor alloy.

24. The asymmetric transistor of claim 18 , wherein said strain-inducing semiconductor alloy comprises at least one of germanium and tin.

25. The asymmetric transistor of claim 18 , wherein said strain-inducing semiconductor alloy comprises carbon.