Work function adjustment in high-k gate stacks including gate dielectrics of different thickness
In sophisticated manufacturing techniques, the work function and thus the threshold voltage of transistor elements may be adjusted in an early manufacturing stage by providing a work function adjusting species within the high-k dielectric material with substantially the same spatial distribution in the gate dielectric materials of different thickness. After the incorporation of the work function adjusting species, the final thickness of the gate dielectric materials may be adjusted by selectively forming an additional dielectric layer so that the further patterning of the gate electrode structures may be accomplished with a high degree of compatibility to conventional manufacturing techniques. Consequently, extremely complicated processes for re-adjusting the threshold voltages of transistors having a different thickness gate dielectric material may be avoided.
1. A method of forming a semiconductor device, the method comprising:
forming a material layer stack above a first device region and a second device region, said material layer stack comprising a dielectric base layer, a high-k dielectric material formed on said dielectric base layer and metal-containing material formed on said high-k dielectric material;
performing a heat treatment so as to diffuse a metal species from said metal-containing material to an interface formed by said dielectric base layer and said high-k dielectric material;
forming a dielectric layer selectively above said second device region after performing said heat treatment; and
forming a first gate electrode structure above said first device region and a second gate electrode structure above said second device region, said first gate electrode structure comprising said dielectric base layer and said high-k dielectric material as a first gate dielectric and said second gate electrode structure comprising said dielectric base layer, said high-k dielectric material and said dielectric layer as a second gate dielectric.
2. The method of claim 1 , wherein forming said dielectric layer selectively above said second device region comprises removing said metal-containing material selectively above said second device region, depositing said dielectric layer above said first and second device region and removing said dielectric layer selectively from above said first device region by using said metal-containing material as an etch stop.
3. The method of claim 2 , wherein said metal-containing material comprises titanium nitride.
4. The method of claim 3 , wherein removing said dielectric layer selectively from above said second device region further comprises performing a wet chemical etch process on the basis of hydrofluoric acid.
5. The method of claim 1 , further comprising removing said metal-containing material after forming said dielectric layer selectively above said second device region and forming a second metal-containing material above said first and second device regions.
6. The method of claim 1 , wherein forming said material layer stack comprises forming a first metal-containing material on said high-k dielectric material and forming a work function adjusting species on said first metal-containing material.
7. The method of claim 1 , wherein said dielectric base layer comprises silicon and oxygen.
8. The method of claim 1 , wherein said dielectric layer comprises silicon dioxide.
9. The method of claim 1 , further comprising forming a first transistor in said first device region on the basis of said first gate electrode structure and forming a second transistor in said second device region on the basis of said second gate electrode structure, wherein said first and second transistors have substantially the same threshold voltage.
10. The method of claim 1 , further comprising removing said metal-containing material from above said first and second device regions and forming a second metal-containing material selectively above said first device region prior to forming said dielectric layer selectively above said second device region.
11. The method of claim 10 , further comprising forming an electrode material on said second metal-containing material above said first device region and forming said electrode material on said dielectric layer above said second device region.
12. The method of claim 11 , further comprising forming a transistor in said first device region on the basis of said first gate electrode structure and forming a resistor in said second device region on the basis of said second gate electrode structure.
13. A method, comprising:
forming a dielectric base layer on a first semiconductor region and a second semiconductor region of a semiconductor device;
forming a high-k dielectric material on said dielectric base layer above said first and second semiconductor regions, said dielectric base layer and said high-k dielectric material forming an interface;
forming a work function adjusting species at said interface above said first and second semiconductor regions;
forming a dielectric material on said high-k dielectric material selectively above said second semiconductor region; and
forming a first gate electrode structure on said first semiconductor region and a second gate electrode structure on said second semiconductor region.
14. The method of claim 13 , further comprising forming a metal-containing material layer on said high-k dielectric material and on said dielectric material.
15. The method of claim 14 , further comprising forming a semiconductor electrode material on said metal-containing material.
16. The method of claim 13 , further comprising forming a metal-containing material selectively on said high-k dielectric material and forming an electrode material on said metal-containing material and on said dielectric material.
17. The method of claim 13 , wherein forming said work function adjusting species at said interface comprises forming a material layer comprising said work function adjusting species on said high-k dielectric layer and annealing said semiconductor device.
18. The method of claim 17 , further comprising removing said material layer and forming a metal-containing material selectively on said high-k dielectric material above said first semiconductor region.
19. The method of claim 18 , wherein said material layer and said metal-containing material comprises titanium nitride.