Field effect transistor with air gap dielectric
View Patent ↗A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.
1. A method of forming a field effect transistor (FET), the method comprising:
forming first and second silicon strips, the first and second strips being substantially parallel to one another and separated from each other;
filling a space between a portion of the first and second silicon strips with an oxide;
covering the oxide with a nitride layer;
forming a hole in the nitride layer;
forming a porous pattern in the nitride layer, forming the pattern including placing a diblock copolymer on top of the nitride layer and, after the diblock copolymer has been self-aligned, etching the nitride through the diblock copolymer;
etching the oxide through the nitride layer to form an airgap below the nitride layer; and
sealing the air gap.
2. The method of claim 1 , further comprising:
forming a layer of thermal oxide on sides of the first and second strips.
3. The method of claim 2 , wherein covering the oxide includes covering the thermal oxide.
4. The method of claim 1 , further comprising:
covering the first and second strips with an oxide layer.
5. The method of claim 1 , wherein sealing includes:
forming a sealing layer by chemically vapor depositing an oxide through the nitride layer.