Non-volatile memory device using hot-carrier injection
Each of a hot-carrier non-volatile memory device and a method for fabricating the hot carrier non-volatile memory device is predicated upon a semiconductor structure and related method that includes a metal oxide semiconductor field effect transistor structure. The semiconductor structure and related method include at least one of: (1) a spacer that comprises a dielectric material having a dielectric constant greater than 7 (for enhanced hot carrier derived charge capture and retention); and (2) a drain region that comprises a semiconductor material that has a narrower bandgap than a bandgap of a semiconductor material from which is comprised a channel region (for enhanced impact ionization and charged carrier generation).
1. A hot carrier non-volatile memory device comprising:
a semiconductor substrate;
a gate dielectric located upon the semiconductor substrate;
a gate located upon the gate dielectric and aligned above a channel region within the semiconductor substrate;
a spacer located upon a sidewall of the gate and contacting the semiconductor substrate, said spacer having a dielectric constant that is greater than 7, wherein the spacer having a dielectric constant that is greater than 7 provides enhanced hot-carrier impact ionized electron capture and retention capabilities in the hot carrier non-volatile memory device that is due to a lower charge carrier injection barrier for the spacer having the dielectric constant that is greater than 7 in comparison to a similarly structured memory device having a silicon oxide spacer; and
a source region and a drain region located within the semiconductor substrate and separated by the channel region, wherein the drain region comprises a semiconductor material having a narrower bandgap than a semiconductor material from which is comprised the channel, wherein the semiconductor material having the narrower bandgap is not present in the source region, wherein the drain region having the semiconductor material of the narrow bandgap provides the hot-carrier non-volatile memory device with increased impact ionization for forming charged carrier pairs in comparison to the similarly structured memory device having a channel region and drain region with a same bandgap, said drain region of the hot carrier non-volatile memory device having an enhanced charged carrier pair generation region beneath the spacer when compared to the similarly structured memory device.
2. The hot carrier non-volatile memory device of claim 1 wherein the semiconductor substrate comprises a bulk semiconductor substrate.
3. The hot carrier non-volatile memory device of claim 1 wherein the semiconductor substrate comprises a semiconductor-on-insulator substrate.
4. The hot carrier non-volatile memory device of claim 1 wherein the semiconductor substrate comprises a hybrid orientation substrate.
5. The hot carrier non-volatile memory device of claim 1 wherein the spacer comprises a dielectric material having a dielectric constant greater than 50.
6. The hot carrier non-volatile memory device of claim 1 wherein the spacer comprises a dielectric material having a dielectric constant greater than 70.
7. The hot carrier non-volatile memory device of claim 1 wherein the spacer comprises a dielectric material having a dielectric constant greater than 100.
8. A method for fabricating a hot carrier non-volatile memory device comprising:
providing a semiconductor substrate;
forming a gate dielectric upon the semiconductor substrate;
forming a gate upon the gate dielectric and aligned above a channel region within the semiconductor substrate;
forming a spacer upon a sidewall of the gate and upon the semiconductor substrate, said spacer having a dielectric constant that is greater than 7, wherein the spacer having a dielectric constant that is greater than 7 provides enhanced hot-carrier impact ionized electron capture and retention capabilities in the hot carrier non-volatile memory device that is due to a lower charge carrier injection barrier for the spacer having the dielectric constant that is greater than 7 in comparison to a similarly structured memory device having a silicon oxide spacer; and
forming a source region and a drain region within the semiconductor substrate and separated by the channel, wherein the drain region comprises a semiconductor material having a narrower bandgap than a semiconductor material from which is comprised the channel, wherein the semiconductor material having the narrower bandgap is not present in the source region, wherein the drain region having the semiconductor material of the narrow bandgap provides the hot-carrier non-volatile memory device with increased impact ionization for forming charged carrier pairs in comparison to the similarly structured memory device having a channel region and drain region with a same bandgap, said drain region of the hot carrier non-volatile memory device having an enhanced charged carrier pair generation region beneath the spacer when compared to the similarly structured memory device.
9. The method of claim 8 wherein the spacer comprises a dielectric material having a dielectric constant greater than 50.
10. The method of claim 8 wherein the spacer comprises a dielectric material having a dielectric constant greater than 70.
11. The method of claim 8 wherein the spacer comprises a dielectric material having a dielectric constant greater than 100.