Scan test circuit, and method and program for designing same

1. A scan test circuit comprising:

a scan path shift register comprising adjacent flip-flops; and

a clock signal supplying unit configured to scan shift clock signals shifted by a half cycle to each of two adjacent said flip-flops constituting said shift register, and of further supplying clock signals shifted by a cycle to each of at least a pair of adjacent flip-flops of said flip-flops, during a shift mode operation,

wherein said clock signal supplying unit is configured so as to alternately supply a clock signal having a positive phase and a clock signal having an opposite phase to each of said flip-flops, and of further supplying a clock signal having the same phase to at least three consecutive flip-flops of said flip-flops.

2. The scan test circuit as defined in claim 1 , wherein said clock signal supplying unit comprises a shift register that holds determination data determining whether the clock signal supplied to said flip-flops has a positive phase or an opposite phase thereof, and controls supply of the clock signal based on said held determination data.

3. The scan test circuit as defined in claim 2 , wherein said shift register is configured so that said determination data can be set externally.

4. The scan test circuit as defined in claim 1 , wherein said clock signal supplying unit is configured as to be capable of supplying a clock signal having the same phase to each of said flip-flops during sample mode operation.

5. A method for implementing a scan test circuit comprising a computer device executing the steps of:

inserting scan test circuit defining a scan path shift register constituted by plural flip-flops with a test target (Lg) connected to data input terminals (DI) of each two adjacent flip-flops, a scan-in signal (SIN) being fed to an input terminal (SI) of a first flip-flop 201 , output terminals of the flip-flops being connected to input terminals (SI) of an adjacent downstream flip-flops respectively, an output signal (SOUT) of a final flip-flop providing a scan test result;

configuring a clock signal supplying unit so as to supply scan shift clock signals shifted by a half cycle to each of the two adjacent flip-flops constituting the scan path shift register;

confirming whether or not said flip-flops have sufficient setup time during a scan shift operation to identify a flip-flop whose setup time is insufficient;

inserting a normal/inverted clock control circuit that generates a clock signal adapted to control shift operation of a flip-flop of which said setup time is insufficient; and

with the inverted clock control circuit, changing a control clock signal for the scan circuit so as to control alternately between normal and inverted clock signals and replacing the control clock signal for the flip-flop of which said setup time is insufficient with an output of said normal/inverted clock control circuit.

6. The method for implementing a scan test circuit as defined in claim 5 , comprising a further step after said step of inserting a shift register that holds control information for said normal/inverted clock control circuit before replacing said control signal in a case where there is a plurality of flip-flops of which said setup time is insufficient when said confirmation is made.

7. The method for implementing a scan test circuit as defined in claim 6 , further comprising performing timing verification again after a layout of said scan test circuit has been completed, and modifying the output of said normal/inverted clock control circuit based on the results of said timing verification.

8. The method for implementing a scan test circuit as defined in claim 5 , comprising the further steps of:

confirming a timing of the scan path shift register after the inverted clock control circuit to provide a timing confirmation result;

determining whether a setup time is sufficient or insufficient according to the timing confirmation result; and

when the setup time is insufficient according to the timing confirmation result, again inserting the inverted/normal clock control circuit to change control of the scan test circuit with insufficient setup time over to a third clock signal.

9. The method for implementing a scan test circuit as defined in claim 5 , comprising the further steps of:

subsequent to said step of changing over to the third clock signal, performing layout processing and timing confirmation;

after said step of layout processing, confirming a further setup time;

determining whether the further setup time is sufficient or insufficient; and

when said further setup time is determining to be insufficient, updating a ClkCtrl control signal information and performing further timing verification,

wherein when said further setup time is sufficient, a semiconductor integrated circuit design test is complete.

10. The method for implementing a scan test circuit as defined in claim 5 , wherein said clock signal supplying unit is configured so as to alternately supply a clock signal having a positive phase and a clock signal having an opposite phase to each of said flip-flops, and of further supplying a clock signal having the same phase to at least three consecutive flip-flops of said flip-flops.

11. A non-transitory computer readable medium storing thereon a computer readable program when executed by a computer causing the computer to execute a circuit design method comprising the steps of:

configuring a clock signal supplying unit so as to supply, to a scan path test register comprising adjacent flip-flops, scan shift clock signals shifted by a half cycle to each of two adjacent said flip-flops constituting the scan path shift register;

confirming whether or not said flip-flops have sufficient setup time during a scan shift operation to identify a flip-flop whose setup time is insufficient; and

inserting a normal/inverted clock control circuit that generates a clock signal adapted to control shift operation of a flip-flop of which said setup time is insufficient, the inverted clock control circuit changing a control clock signal for the scan circuit so as to control alternately between normal and inverted clock signals and replacing the control signal for the flip-flop of which said setup time is insufficient with an output of said normal/inverted clock control circuit.

12. The non-transitory computer readable medium as defined in claim 11 , having the computer execute inserting a shift register that holds control information for said normal/inverted clock control circuit before replacing said control signal in a case where there is a plurality of flip-flops of which said setup time is insufficient when said confirmation is made.

13. The non-transitory computer readable medium as defined in claim 12 , having the computer further execute performing timing verification again after the layout of said scan test circuit has been completed, and modifying the output of said normal/inverted clock control circuit based on the results of said timing verification.

14. The non-transitory computer readable medium as defined in claim 11 , wherein said clock signal supplying unit is configured so as to alternately supply a clock signal having a positive phase and a clock signal having an opposite phase to each of said flip-flops, and of further supplying a clock signal having the same phase to at least three consecutive flip-flops of said flip-flops.