Field-effect transistor device having a metal gate stack with an oxygen barrier layer

1. A field effect transistor device comprising:

a semiconductor substrate;

a gate stack comprising:

a gate dielectric layer overlaying the semiconductor substrate;

an electrically conductive oxygen barrier layer overlaying the gate dielectric layer;

a low resistivity metal layer overlaying the oxygen barrier layer, wherein each layer in the gate stack has less than 90 atom percent of silicon, germanium or silicon and germanium combined; and

a conducting material layer between the gate dielectric layer and the oxygen barrier layer;

a spacer adjacent to the gate stack and in direct contact with each layer of the gate stack; and

an encapsulation layer on a top of the gate stack and in contact with the low resistivity metal layer, the encapsulation layer adjacent to the spacer and in direct contact with the spacer.

2. The field effect transistor device of claim 1 wherein the gate dielectric layer is a high dielectric constant gate dielectric layer.

3. The field effect transistor device of claim 1 wherein the low resistivity metal layer is selected from the group consisting of tungsten (W) and tantalum (Ta).

4. The field effect transistor device of claim 1 wherein the conducting material layer is selected from the group consisting of titanium nitride, tantalum nitride, titanium silicon nitride, tantalum silicon nitride, titanium carbide, tantalum carbide and combinations thereof.

5. The field effect transistor device of claim 1 wherein the encapsulation layer is selected from the group consisting of silicon nitride, aluminum oxide, hafnium oxide, and zirconium oxide.

6. The field effect transistor device of claim 1 wherein the oxygen barrier layer is selected from the group consisting of titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), hafnium (Hf), zirconium (Zr), hafnium silicide (HfSix), zirconium silicide (ZrSix), titanium silicide (TiSix), niobium-doped titanium silicide, tungsten silicide (WSix), hafnium nitride (HfN), hafnium silicon nitride (HfSiN), zirconium nitride (ZrN), and titanium hafnium nitride (TiHfN).

7. A field effect transistor device comprising:

a semiconductor substrate;

a gate stack comprising:

a gate dielectric layer overlaying the semiconductor substrate;

an electrically conductive oxygen barrier layer overlaying the gate dielectric layer;

a low resistivity metal layer overlaying the oxygen barrier layer, wherein each layer in the gate stack has less than 90 atom percent of silicon, germanium or silicon and germanium combined;

an electrically conducting layer on the low resistivity metal layer; and

a conducting material layer between the gate dielectric layer and the oxygen barrier layer; and

a spacer adjacent to the gate stack and in direct contact with each layer of the gate stack.

8. A method for fabricating a field effect transistor device comprising the steps of:

forming a gate stack on a semiconductor substrate comprising the steps of:

forming a gate dielectric layer over the semiconductor substrate;

forming a conducting material layer over the gate dielectric layer;

forming an electrically conductive oxygen barrier layer over the conducting material layer; and

forming a low resistivity layer over the oxygen barrier layer, wherein each layer in the gate stack has less than 90 atom percent of silicon, germanium or silicon and germanium combined;

forming a spacer adjacent to the gate stack and in direct contact with each layer of the gate stack;

forming an encapsulation layer overlaying the gate stack in contact with the low resistivity layer and in direct contact with the spacer; and

performing a dopant activation anneal.

9. The method of claim 8 wherein the dopant anneal is an anneal at a temperature greater than 950 C.

10. The method of claim 8 wherein the low resistivity metal layer is selected from the group consisting of tungsten (W) and tantalum (Ta).

11. The method of claim 8 wherein the conducting material layer is selected from the group consisting of titanium nitride, tantalum nitride, titanium silicon nitride, tantalum silicon nitride, titanium carbide, tantalum carbide and combinations thereof.

12. The method of claim 8 wherein the encapsulation layer is selected from the group consisting of silicon nitride, aluminum oxide, hafnium oxide, and zirconium oxide.

13. The method of claim 8 wherein the oxygen barrier layer is selected from the group consisting of titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), hafnium (Hf), zirconium (Zr), hafnium silicide (HfSix), zirconium silicide (ZrSix), titanium silicide (TiSix), niobium-doped titanium silicide, tungsten silicide (WSix), hafnium nitride (HfN), hafnium silicon nitride (HfSiN), zirconium nitride (ZrN), and titanium hafnium nitride (TiHfN).

14. The method of claim 8 wherein the oxygen barrier layer is hafnium nitride.

15. A method for fabricating a field effect transistor device comprising the steps of:

forming a gate stack on a semiconductor substrate comprising the steps of:

forming a gate dielectric layer over the semiconductor substrate;

forming a conducting material layer over the gate dielectric layer;

forming an electrically conductive oxygen barrier layer over the conducting material layer;

forming a low resistivity layer over the oxygen barrier layer, wherein each layer in the gate stack has less than 90 atom percent of silicon, germanium or silicon and germanium combined; and

forming an electrically conducting layer over the low resistivity metal layer in the gate stack;

forming a spacer adjacent to the gate stack and in direct contact with each layer of the gate stack; and

performing a dopant activation anneal.