Metal cap layer with enhanced etch resistivity for copper-based metal regions in semiconductor devices
During the fabrication of sophisticated metallization systems of semiconductor devices, material deterioration of conductive cap layers may be significantly reduced by providing a noble metal on exposed surface areas after the patterning of the corresponding via openings. In one embodiment, a semiconductor device is provided that includes a metallization system formed above a substrate. The metallization system includes a metal line formed in a dielectric layer and having a top surface. The metallization system also includes a conductive cap layer formed on the top surface. A via extends through the conductive cap layer and connects to the top surface of the metal line. A conductive barrier layer is formed on sidewalls of the via. An interface layer is formed of a noble metal between the conductive cap layer and the conductive barrier layer and between the top surface of the metal line and the conductive barrier layer.
1. A semiconductor device, comprising:
a metallization system positioned above a substrate, said metallization system comprising:
a metal line positioned in a dielectric layer and having a top surface, said metal line being comprised of a first metal material;
a conductive cap layer positioned above said top surface, said conductive cap layer being comprised of a second metal material other than said first metal material;
an etch stop layer is positioned above the conductive cap layer and substantially coplanar with and adjacent to a top surface of the dielectric layer;
a via extending through said conductive cap layer and said etch stop layer and connecting to said top surface of said metal line, said via comprising a conductive barrier layer at least on sidewalls thereof; and
an interface layer positioned between said conductive cap layer and said conductive barrier layer and between said top surface of the metal line and said conductive barrier layer, said interface layer comprised of a metal that is more noble than a metal of said conductive cap layer, wherein the interface layer is substantially restricted to a height that is equal to or less than a height level defined by a thickness of said etch stop layer.
2. The semiconductor device of claim 1 , wherein said metal of said interface comprises at least one of ruthenium, iridium and platinum.
3. The semiconductor device of claim 1 , wherein said second metal material comprises an alloy including cobalt.
4. The semiconductor device of claim 3 , wherein said alloy is a ternary alloy.
5. The semiconductor device of claim 3 , wherein said second metal material is comprised of an alloy including cobalt, tungsten and phosphorous.
6. The semiconductor device of claim 1 , wherein said dielectric layer comprises a low-k dielectric material having a dielectric constant of approximately 2.7 and less.
7. The semiconductor device of claim 1 , wherein said metal line is comprised of copper.
8. The semiconductor device of claim 1 , further comprising transistor elements having a critical dimension of 50 nm or less.
9. A semiconductor device, comprising:
a metallization system positioned above a substrate, said metallization system comprising:
a metal line positioned in a dielectric layer and having a top surface, said metal line being comprised of a first metal material;
a conductive cap layer positioned above said top surface, said conductive cap layer being comprised of a second metal material other than said first metal material;
an etch stop layer positioned over the conductive cap layer and substantially coplanar with and adjacent to a top surface of the dielectric layer;
a via extending through said conductive cap layer and said etch stop layer and connecting to said top surface of said metal line, said via comprising a conductive barrier layer at least on sidewalls thereof; and
an interface layer adjacent sidewalls of said conductive cap layer in said via and between said conductive cap layer and said conductive barrier layer, wherein the interface layer is adjacent a portion of said top surface of said metal line and between said top surface of the metal line and said conductive barrier layer, said interface layer comprised of a metal that is more noble than a metal of said conductive cap layer, wherein the interface layer is substantially restricted to a height that is equal to or less than a height level defined by a thickness of said etch stop layer.
10. The semiconductor device of claim 9 , wherein said metal of said interface comprises at least one of ruthenium, iridium and platinum.
11. The semiconductor device of claim 9 , wherein said second metal material comprises an alloy including cobalt.
12. The semiconductor device of claim 11 , wherein said alloy is a ternary alloy.
13. The semiconductor device of claim 11 , wherein said second metal material is comprised of an alloy including cobalt, tungsten and phosphorous.
14. The semiconductor device of claim 9 , wherein said dielectric layer comprises a low-k dielectric material having a dielectric constant of approximately 2.7 and less.
15. The semiconductor device of claim 9 , wherein said metal line is comprised of copper.
16. The semiconductor device of claim 9 , further comprising transistor elements having a critical dimension of 50 nm or less.