I/O circuit with phase mixer for slew rate control

1. An apparatus, comprising:

a first phase mixer coupled to a first driver line, the first phase mixer including a first output, the first phase mixer operable to:

receive an enable signal and a first delayed enable signal, the first delayed enable signal derived from the enable signal;

generate a first signal on the first driver line, wherein the first signal having a first delay with respect to the first enable signal by mixing the enable signal and the first delayed enable signal;

provide a second delayed enable signal at the first output; and

a second phase mixer coupled to a second driver line, the second phase mixer including a second output, the second phase mixer operable to:

receive the enable signal and the second delayed enable signal from the first phase mixer;

generate a second signal on the second driver line, wherein the second signal having a second configurable delay with respect to the enable signal by mixing the enable signal and the second delayed enable signal; and

provide the first delayed enable signal at the second output.

2. The apparatus of claim 1 , further comprising a plurality of driver lines operable to drive a terminal to a logic state based on the enable signal, wherein the plurality of driver lines includes the first driver line and the second driver line.

3. The apparatus of claim 1 , wherein the first phase mixer comprises a plurality of stages, each of the plurality of stages being operable to select one of the enable signal and the first delayed enable signal based on a corresponding bit of a first control word, and wherein the first phase mixer is further operable to mix the selections of each of the plurality of stages to generate the first signal.

4. The apparatus of claim 3 , wherein the plurality of stages is a first plurality of stages, and the second phase mixer comprises a second plurality of stages, each of the second plurality of stages being operable to select one of the enable signal and the second delayed enable signal based on a corresponding bit of a second control word, and wherein the second phase mixer is further operable to mix the selections of each of the second plurality of stages to generate the second signal.

5. The apparatus of claim 3 , wherein each of the first plurality of stages selects the enable signal.

6. The apparatus of claim 1 , wherein the first driver line and the second driver line are associated with a pull-up path coupled to a terminal, and wherein the enable signal comprises a pull-up enable signal.

7. The apparatus of claim 1 , further comprising timing adjust circuitry coupled to the first phase mixer and to the second phase mixer, the timing adjust circuitry operable to provide an additional variable delay on each of the first driver line and the second driver line.

8. The apparatus of claim 7 , further comprising at least one buffer coupled to a third driver line and to the timing adjust circuitry, wherein the timing adjust circuitry is further operable to provide an additional variable delay on the third driver line.

9. An apparatus comprising:

a first phase mixer coupled to a first driver line, the first phase mixer including a first output, the first phase mixer operable to:

receive an enable signal and a first delayed enable signal, the first delayed enable signal derived from the enable signal;

generate a first signal on the first driver line having a first delay with respect to the first enable signal by mixing the enable signal and the first delayed enable signal;

provide a second delayed enable signal at the first output;

at least one buffer coupled to a second driver line; and

timing adjust circuitry coupled to the first phase mixer and the at least one buffer, the timing adjust circuitry operable to provide an additional variable delay on each of the first drive line and the second driver line.

10. The apparatus of claim 9 , further comprising a pull-up driver coupled to the timing adjust circuitry and operable to drive an output line high responsive to the enable signal.

11. The apparatus of claim 9 , wherein a resolution of the additional variable delay is less than a resolution of the first delay.

12. A method comprising:

receiving an enable signal at a first phase mixer,

receiving a first delayed enable signal at the first phase mixer from a second phase mixer, wherein the first delayed enable signal is generated by the second phase mixer based on a second drive signal;

mixing the enable signal and the first delayed enable signal to generate a drive signal; and

driving a terminal to a first logic state based on the drive signal; and

providing a second delayed enable signal to the second phase mixer based on the drive signal, wherein the second drive signal is based on the enable signal and the second delay enable signal.

13. The method of claim 12 , further comprising receiving a control word at the first phase mixer, wherein the first enable signal and the first delayed enable signal are mixed based on the control word.

14. The method of claim 12 , wherein mixing the first enable signal and the first delayed enable signal further comprises:

selecting, at each of a plurality of stages of the first phase mixer, one of the enable signal and the first delayed enable signal based on a corresponding bit of the control word; and

mixing the selection of each of the plurality of stages of the first phase mixer to generate to the drive signal.

15. The method of claim 14 , wherein each of the plurality of stages selects the enable signal.

16. The method of claim 12 , wherein the enable signal comprises a pull-up enable signal.

17. A method comprising:

receiving an enable signal at an enable driver,

mixing, at the enable driver, the enable signal and a first delayed enable signal to generate a first drive signal;

mixing, at the enable driver, the enable signal and a second delayed enable signal to generate a second drive signal;

generating, at the enable driver, the first delayed enable signal based on the second drive signal;

generating, at the enable driver, the second delayed enable signal based on the first drive signal; and

driving a terminal to a first logic state based on at least one of the first drive signal and the second drive signal.

18. The method of claim 17 , further comprising adjusting a slew rate of an output signal based on the first logic state of the terminal.

19. The method of claim 17 , further comprising buffering the enable signal to generate a third drive signal for a third driver line.

20. The method of claim 17 , further comprising delaying at least one of the first drive signal and the second drive signal at a timing adjust circuit of the enable driver.

21. The method of claim 17 , wherein the enable driver is a pull-up enable driver.