IP Library Granted Patent US 8,461,056
Granted Patent B1
US 8,461,056 · App. 13/327,157 · Granted Jun 11, 2013

Self-aligned wet etching process

Inventors: Wei-Che Chang (Taichung, TW); Chun-Hua Huang (Taichung, TW); Chung-Yung Ai (Taichung, TW); Wei-Chih Liu (Taichung, TW); Hsuan-Yu Fang (Taichung, TW); Yu-Ling Huang (Taichung, TW); Meng-Hsien Chen (Taichung, TW); Chun-Chiao Tseng (Taichung, TW); Yu-Shan Hsu (Taichung, TW); Kazuaki Takesako (Taichung, TW); Hirotake Fujita (Taichung, TW); Tomohiro Kadoya (Taichung, TW); Wen Kuei Hsu (Taichung, TW); Chih-Wei Hsiung (Taichung, TW); Yukihiro Nagai (Taichung, TW); Yoshinori Tanaka (Taichung, TW)
Assignee: Rexchip Electronics Corporation
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Quick Facts
Patent No.
US 8,461,056
App. No.
13/327,157
Granted
Jun 11, 2013
Kind
B1
Abstract

A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.

Claims (13)

1. A self-aligned wet etching process, comprising the steps of:

Step S 1 : etching a substrate including an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other;

Step S 2 : sequentially forming an insulating layer and an etch stop layer on a surface of each of the plurality of trenches to form an accommodation space inside the etch stop layer;

Step S 3 : filling a primary insulator inside the accommodation space, wherein the primary insulator integrates with the etch stop layer and the insulating layer to form a multi-layer isolator;

Step S 4 : removing the etch protection layer to expose a portion of the isolator outside the substrate;

Step S 5 : removing the insulating layer exposing outside the substrate through a wet etching solution, wherein the primary insulator is protected by the etch stop layer and exempted from being etched by the wet etching solution;

Step S 6 : removing the etch stop layer exposing outside the substrate to expose a portion of the primary insulator outside the substrate; and

Step S 7 : forming a plurality of electric contactors on the substrate that are separated by the primary insulator,

wherein in the Step S 1 , the substrate is etched in a first direction and a second direction vertical to the first direction to respectively form a plurality of first trenches spaced from each other and a plurality of second trenches spaced from each other with a plurality of pillars formed between the plurality of first trenches and the plurality of second trenches.

2. The self-aligned wet etching process according to claim 1 , wherein the substrate is made of silicon, and wherein the etch protection layer and the etch stop layer are made of silicon nitride, and wherein the insulating layer and the primary insulator are made of silicon dioxide, and wherein the plurality of electric contactors are made of polysilicon.

3. The self-aligned wet etching process according to claim 1 further comprising a Step S 8 executed after the Step S 7 to flatten the surfaces of the primary insulators and the electric contactors far from the substrate via chemical mechanical polishing.

4. The self-aligned wet etching process according to claim 1 , wherein in the Step S 2 , the insulating layer and the etch stop layer are formed on a surface of each of the plurality of first trenches.

5. The self-aligned wet etching process according to claim 1 , wherein the plurality of pillars are doped with ions.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2015
From: MICRON MEMORY TAIWAN CO., LTD.,
To: MICRON TECHNOLOGY, INC
Reel/Frame 037222/0690 →
CHANGE OF NAME Recorded Dec 7, 2015
From: REXCHIP ELECTRONICS CO., LTD.
To: MICRON MEMORY TAIWAN CO., LTD.
Reel/Frame 037223/0279 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2011
From: CHANG, WEI-CHE; HUANG, CHUN-HUA; AI, CHUNG-YUNG; LIU, WEI-CHIH; FANG, HSUAN-YU; HUANG, YU-LING; CHEN, MENG-HSIEN; TSENG, CHUN-CHIAO; HSU, YU-SHAN; TAKESAKO, KAZUAKI; FUJITA, HIROTAKE; KADOYA, TOMOHIRO; HSU, WEN KUEI; HSIUNG, CHIH-WEI; NAGAI, YUKIHIRO; TANAKA, YOSHINORI
To: REXCHIP ELECTRONICS CORPORATION
Reel/Frame 027389/0288 →