Non-volatile memory with multi-gear control using on-chip folding of data
A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host.
1. A method of operating a memory system including a controller and a non-volatile memory circuit, the non-volatile memory circuit having a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format, and the controller managing the storage of data on the non-volatile memory circuit and the transfer of data between the memory system and a host system, the method comprising:
receiving data from the host;
performing a binary write operation of the received data to the first section of the non-volatile memory circuit;
subsequently folding portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes:
reading the portions of the data from multiple locations in the first section into the read/write registers; and
performing a multi-state programming operation of the potions of the data from the read/write registers into a location the second section of the non-volatile memory,
determining in the controller to operate the memory system according to one of a plurality of modes, including a first mode, wherein the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, wherein the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher rate than in the first mode;
operating the memory system according to determined mode;
wherein the non-volatile memory circuit comprises a plurality of non-volatile memory cells formed along a plurality of word lines and a plurality of bits lines formed as plurality of erase blocks, and wherein the physical pages of the first and second portions belong to differing erase blocks that share a common set of bit lines; and
wherein the memory system operates according to the second mode based on the number of available blocks in the first portion; and
wherein multi-state programming operations include a first phase and a second phase, and during the first mode one or more binary write operations to the first section of the memory are performed between the phases of the multi-state programming operations.
2. The method of claim 1 , wherein the second section store data in an N-bit per cell format,
wherein the data received from the host corresponds to multiple logical pages of data and the binary write operation stores each of the logical pages of data from the read/write registers to a physical page in the first section of the non-volatile memory circuit, and
wherein the folding operation includes:
reading N logical pages from a corresponding N physical pages in the first section into the data read/write registers; and
performing the multi-state programming operation of the N logical pages of data from the read/write registers into a physical page of the second section of the non-volatile memory.
3. The method of claim 1 , wherein the plurality of modes includes a third mode, wherein folding operations are background operations executed when the memory system is not receiving data from the host.
4. A method of operating a memory system including a controller and a non-volatile memory circuit, the non-volatile memory circuit having a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format, and the controller managing the storage of data on the non-volatile memory circuit and the transfer of data between the memory system and a host system, the method comprising:
receiving data from the host;
performing a binary write operation of the received data to the first section of the non-volatile memory circuit;
subsequently folding portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes:
reading the portions of the data from multiple locations in the first section into the read/write registers; and
performing a multi-state programming operation of the potions of the data from the read/write registers into a location the second section of the non-volatile memory,
determining in the controller to operate the memory system according to one of a plurality of modes, including a first mode, wherein the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, wherein the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher rate than in the first mode;
operating the memory system according to determined mode;
wherein the memory system is operated according to the first mode in response to the controller determining that data received from the host is for logically sequential pages of data; and
wherein multi-state programming operations include a first phase and a second phase, and during the first mode one or more binary write operations to the first section of the memory are performed between the phases of the multi-state programming operations.
5. The method of claim 4 , wherein the second section store data in an N-bit per cell format,
wherein the data received from the host corresponds to multiple logical pages of data and the binary write operation stores each of the logical pages of data from the read/write registers to a physical page in the first section of the non-volatile memory circuit, and
wherein the folding operation includes:
reading N logical pages from a corresponding N physical pages in the first section into the data read/write registers; and
performing the multi-state programming operation of the N logical pages of data from the read/write registers into a physical page of the second section of the non-volatile memory.
6. The method of claim 4 , further comprising:
subsequently determining to operate the memory system according to a different one of the modes; and
operating the memory according to the subsequently determined different mode.
7. The method of claim 4 , wherein the plurality of modes includes a third mode, wherein folding operations are background operations executed when the memory system is not receiving data from the host.
8. The method of claim 4 , wherein the multi-state programming operation uses a foggy-fine programming algorithm and the first phase includes a foggy programming operation and the second phase is a fine programming operation.
9. The method of claim 4 , wherein the first phase further includes an initial programming operation prior to the foggy programming operation.
10. The method of claim 4 , wherein the memory further includes a volatile buffer memory, the method further including:
subsequent to receiving each logical pages of data from a host, storing the logical pages of data in the buffer memory before performing a binary write operation of each of the received logical pages, wherein the transfers of data from the host to the buffer memory is performed concurrently with a multi-state programming operation.
11. The method of claim 4 , wherein the non-volatile memory circuit comprises a plurality of non-volatile memory cells formed along a plurality of word lines and a plurality of bits lines formed as plurality of erase blocks, and wherein the physical pages of the first and second portions belong to differing erase blocks that share a common set of bit lines.
12. The method of claim 4 , wherein the memory system operates according to the second mode in response to the controller determining that data received from the host is for logically non-sequential pages of data.
13. The method of claim 4 , wherein the memory system operates according to the second mode in response to a program failure.
14. The method of claim 4 , further comprising:
in response to determining to operate the memory system according to the second mode, sending a request to the host to reduce the rate at which the host transfers data to the memory system.
15. The method of claim 4 , wherein the memory system operates according to the second mode in response to receiving a command from set of one or more commands.
16. The method of claim 4 , wherein the memory system operates according to the second mode in response to the controller determining that the host has sent a command for writing control data.
17. The method of claim 16 , wherein the control data is logical to physical address translation information.
18. The method of claim 4 , wherein the memory system operates according to the second mode in response to receiving a write command for a predetermined address.