IP Library Granted Patent US 8,482,115
Granted Patent B2
US 8,482,115 · App. 12/789,203 · Granted Jul 9, 2013

Integrated circuit packaging system with dual side connection and method of manufacture thereof

Inventor: Reza Argenty Pagaila (Singapore, SG)
Assignee: STATS ChipPAC Ltd.
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Quick Facts
Patent No.
US 8,482,115
App. No.
12/789,203
Granted
Jul 9, 2013
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; pressing an encapsulation onto the package carrier and with the integrated circuit therein; mounting a conductive frame, having a vertical pillar integral with a horizontal cover, through the encapsulation, over the integrated circuit, and the vertical pillar on the package carrier and the horizontal cover on the encapsulation; and forming a contact from the horizontal cover.

Claims (15)

1. An integrated circuit packaging system comprising:

a package carrier;

an integrated circuit over the package carrier;

an encapsulation onto the package carrier and with the integrated circuit therein; and

a support terminal, having a vertical pillar and a contact horizontally offset from the vertical pillar, wherein the vertical pillar extends through the encapsulation and onto the package carrier, wherein the contact resides on the encapsulation and over the integrated circuit, the contact having a groove with a curve shape, and wherein the groove, the contact and the vertical pillar are formed from a single structure.

2. The system as claimed in claim 1 wherein:

the package carrier has a recess; and

the integrated circuit is within the recess.

3. The system as claimed in claim 1 further comprising an underfill between the package carrier and the integrated circuit.

4. The system as claimed in claim 1 wherein:

the package carrier has a carrier pad; and

the support terminal, having the vertical pillar integral with the contact, the vertical pillar on the carrier pad.

5. The system as claimed in claim 4 further comprising a resist material over the encapsulation and adjacent to the contact.

6. The system as claimed in claim 4 wherein the integrated circuit has a through silicon via connected to the contact.

7. The system as claimed in claim 4 wherein the integrated circuit is a flip-chip over the package carrier.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0235. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0741 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0235 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2010
From: PAGAILA, REZA ARGENTY
To: STATS CHIPPAC LTD.
Reel/Frame 024540/0908 →
Continuity (1)
Related Publication 20110291257A1 · Dec 1, 2011