Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor device
A method and circuit for implementing die stacking to distribute a logical function over multiple dies, die identification and sparing in through-silicon-via stacked semiconductor devices, and a design structure on which the subject circuit resides are provided. Each die in the die stack includes predefined functional logic for implementing a respective predefined function. The respective predefined function is executed in each respective die and a respective functional result is provided to an adjacent die in the die stack. Each die in the die stack includes logic for providing die identification. An operational die signature is formed by combining a plurality of selected signals on each die. A die signature is coupled to a next level adjacent die using TSV interconnections where it is combined with that die signature.
1. A computer-implemented method for implementing stacking distribution of a logical function over multiple dies in through-silicon-via (TSV) stacked semiconductor devices, a computer performing the steps of said computer-implemented method comprising:
using the computer, providing predefined functional logic for implementing a respective predefined function included in each respective die in a die stack;
arranging each respective die in the die stack for executing the respective predefined function and providing a respective functional result signal output to a next level adjacent die in the die stack using TSV interconnections for combining the respective functional result signal output with the respective predefined functional logic of the next level adjacent die;
providing die identification logic included in each respective die in a die stack; forming an operational die signature by combining a plurality of selected signals on each die; and to provide a die signature to a next level adjacent die in the die stack using TSV interconnections combining the die signature with the die signature of the next level adjacent die; and
identifying a de-selected die in the die stack, and using a spare die in the die stack bypassing the identified de-selected die.
2. The computer-implemented method as recited in claim 1 includes providing sparing logic included in the die stack, and storing the spare die information in a fuse coupled to the sparing logic.
3. The computer-implemented method as recited in claim 1 wherein the respective predefined functional logic includes an adder function included on each die.
4. The computer-implemented method as recited in claim 1 wherein the respective predefined functional logic includes an inverter function included on each die.