ETSOI with reduced extension resistance

1. A method of fabricating a semiconductor device, the method comprising:

forming an SOI substrate;

epitaxially forming a silicon-containing layer on the SOI substrate;

forming a gate dielectric layer and gate electrode on the epitaxially formed silicon-containing layer;

forming a first spacer on each side of the gate dielectric layer and gate electrode;

removing the gate dielectric layer and gate electrode, thereby exposing a portion of the silicon-containing layer; and

removing the exposed portion of the silicon-containing layer.

2. The method according to claim 1 , wherein the SOI substrate comprises a thin silicon layer on a silicon substrate with a buried oxide layer (BOX) in between, the thin silicon layer having a thickness of about 6 nm to about 8 nm.

3. The method according to claim 1 , further comprising:

forming raised source/drain regions adjacent each first spacer.

4. The method according to claim 3 , comprising forming the source/drain regions as faceted source/drain regions.

5. The method according to claim 3 , further comprising:

forming a second spacer on each first spacer; and

forming a silicide on the source/drain regions.

6. The method according to claim 1 , wherein removing the exposed portion of the silicon-containing layer comprises:

selectively etching the silicon-containing layer; and

stopping on the SOI substrate.

7. The method according to claim 1 , further comprising forming a replacement gate electrode on the SOI substrate between the first spacers after removing the exposed portion of the silicon containing layer.

8. The method according to claim 7 , wherein the replacement gate electrode comprises a high-k dielectric layer and a metal gate electrode.

9. The method according to claim 1 , comprising forming the silicon-containing layer by epitaxially growing silicon germanium to a thickness of about 8 nm to about 12 nm.

10. A method of fabricating a semiconductor, the method comprising:

forming an ETSOI substrate;

epitaxially growing silicon germanium on the ETSOI substrate to a thickness of about 8 nm to about 12 nm;

forming a gate dielectric layer and a gate electrode on the epitaxially formed silicon-containing layer;

forming a first spacer on each side of the gate dielectric layer and the gate electrode;

epitaxially forming a raised and faceted source/drain region on the silicon-containing layer, adjacent each first spacer;

removing the gate dielectric layer and the gate electrode, thereby exposing a portion of the silicon-containing layer;

selectively etching exposed portion of the silicon-containing layer, stopping on the ETSOI substrate;

forming a high-k dielectric layer and a metal gate electrode on the ETSOI substrate between the first spacers.

11. The method according to claim 1 , comprising forming the silicon-containing layer by epitaxially growing carbon-doped silicon (Si:C) to a thickness of about 8 nm to about 12 nm.

12. The method according to claim 1 , comprising forming the gate dielectric layer and the gate electrode by:

depositing a dielectric layer on the silicon-containing layer;

depositing an amorphous silicon or polysilicon layer on the dielectric layer; and

etching the dielectric layer and the amorphous silicon or polysilicon layer, leaving only a gate electrode and an underlying gate dielectric layer.